H03M13/37

Context-dependent shared dictionaries
11669553 · 2023-06-06 · ·

An context-based encoding mechanism uses a predetermined number of bytes in a previous segment of a file to determine a context for the current segment. The current segment is encoded using a dictionary that corresponds to the determined context. An example method includes determining, for a first segment in a data file, a first context state based on a first context segment within the data file that precedes the first segment, identifying a first indexed dictionary from a plurality of indexed dictionaries based on the first context state, and encoding the first segment using the identified first indexed dictionary.

Context-dependent shared dictionaries
11669553 · 2023-06-06 · ·

An context-based encoding mechanism uses a predetermined number of bytes in a previous segment of a file to determine a context for the current segment. The current segment is encoded using a dictionary that corresponds to the determined context. An example method includes determining, for a first segment in a data file, a first context state based on a first context segment within the data file that precedes the first segment, identifying a first indexed dictionary from a plurality of indexed dictionaries based on the first context state, and encoding the first segment using the identified first indexed dictionary.

Compact timestamp, encoders and decoders that implement the same, and related devices, systems and methods
11671520 · 2023-06-06 · ·

Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.

Data interpretation with modulation error ratio analysis
11494249 · 2022-11-08 · ·

Methods and systems for analyzing data are disclosed. An example method can comprise receiving a first data signal, decoding the first data signal, determining a second data signal based on the decoded first data signal, and determining a modulation error ratio based on a difference between the first data signal and the second data signal.

Decoding apparatus, device, method and computer program
11265016 · 2022-03-01 · ·

Examples relate to a decoding apparatus, a decoding device, a decoding method, a decoding computer program, and a communication device, a memory device and a storage device comprising such a decoding apparatus or decoding method. A decoding apparatus for performing iterative decoding on a codeword comprises processing circuitry comprising a plurality of processing units, and control circuitry configured to control the iterative decoding of the codeword. The iterative decoding is based on a parity-check matrix. The matrix is sub-divided into two or more partitions. The control circuitry is configured to operate in a first mode of operation to process a codeword having a first length, and to operate in a second mode of operation to process a codeword having a second length. The control circuitry is configured to multiplex the utilization of the plurality of processing units across the two or more partitions of the matrix at least in the second mode of operation.

Method and apparatus for vertical layered decoding of quasi-cyclic low-density parity check codes using predictive magnitude maps

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.

METHODS AND DEVICES FOR ERROR CORRECTING CODES DECODING

Embodiments of the invention provide a check node processing unit implemented in a decoder, said decoder being configured to decode a signal encoded using an error correcting code, said signal comprising symbols, the check node processing unit being configured to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components, each component comprising a value of a symbol and a reliability metrics associated with said symbol, wherein the check node processing unit comprises: a data structure (31) configured to store said input messages, the components of the input messages being associated with an integer index in the data structure; a data processing unit (33) configured to apply one or more iterations of a transformation operation to at least a part of the data structure, each iteration of the transformation operation being performed to arrange the components of said input messages in said data structure (31) depending on at least some of the components of the messages associated with a given value of the integer index, which provides a transformed data structure; a calculation unit (35) configured to determine said at least one output message from the components comprised in said transformed data structure.

Controller of nonvolatile semiconductor memory

According to one embodiment, a controller includes a decoder, calculation section, table creation, and control section. The decoder converts ECC frames into likelihood information based on a set table, generates decoded ECC frames by decoding using the likelihood information and switches the set table when there is an ECC frame in which the decoding is unsuccessful. The calculation section generates calculation data based on an ECC frame of calculation target among the decoded ECC frames and its ECC frame before decoded. The table creation section sets the new table to the decoder based on the calculation data. The control section controls the calculation target so that a calculation in the calculation section is not repeated for an ECC frame in which the decoding is successful.

Combined asynchronous and synchronous fountain code storage in an object store
09798617 · 2017-10-24 · ·

Example apparatus and methods produce a set of rateless erasure codes (e.g., fountain codes) for a file stored in a primary data store (e.g., hard drive) or in an archive system. The archive system may store the file in a redundant array of independent disks (RAID). A first subset of the rateless erasure codes are stored in an object storage using a synchronous protocol. A second subset of rateless erasure codes are stored in the object storage using an asynchronous protocol. The object storage system may inform the archive system when desired redundancy has been achieved or when desired redundancy has been lost. The archive system may buffer rateless erasure codes before providing the codes to the object storage to improve performance. A failure in the archive system or object storage system may be mitigated by retaining the file in the primary data store until the desired redundancy is achieved.

Controller, semiconductor memory system and operating method thereof
09798614 · 2017-10-24 · ·

An operating method of a controller includes generating error reliability of data based on reliability information of one or more error-corrected bits of the data, wherein the data is read out from a semiconductor memory device and a hard decision ECC decoding to the data through a BCH code is determined as successful; and determining miscorrection of the data based on the error reliability.