Example apparatus and methods monitor conditions in an object storage system. The conditions monitored may include a load balance measure in the system, a capacity balance measure in the system, a fault tolerance measure in the system, or a usage pattern measure in the system. A distribution plan or redistribution plan for storing or moving erasure codes in the object storage system may be determined based on the conditions. The distribution plan or the redistribution plan for the erasure codes may be updated dynamically in response to changing conditions in the object storage system. The distribution or redistribution may depend on a weighted combination of the load balance measure, the capacity balance measure, the fault tolerance measure, or the usage pattern measure so that responding to one sub-optimal condition (e.g., load imbalance) does not create a different sub-optimal condition (e.g., unacceptable fault tolerance).

Methods for data storage on polymers are provided. In various embodiments, an erasure error correcting code is selected. Input data is read from an input file. The erasure error correcting code is applied to the input data to generate a code word. The code word is encoded according to a chemical alphabet. A number of cycles required for synthesis is determined for the code word. The encoded code word is screened according to the number of cycles. The code word is retained where passing the screening.

A memory device includes a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform coarse decoding and fine decoding. In coarse decoding, the decoder decodes in parallel two or more codewords, which share a common block of bits, to determine error information. Next, the decoder corrects errors in a first codeword based on the error information. Then, it is determined if the shared common block of data bits is corrected. If the shared common data block is updated, then error correction based on the error information is prohibited in codewords sharing the common block of data bits with the first codeword. In fine decoding, a single codeword is decoded at a time for error correction.

An arrangement for decoding a data word using a Reed-Muller code, has: (1) N input terminals, (2) a first level of E>>D summing modules, each summing module being linked with F different input terminals and each input terminal being linked with E summing modules, (3) a first level of E decision modules, each of the D inputs of each decision module being linked respectively with an output from D different summing modules, (4) a second level of H summing modules, (5) a second level of G decision modules, (6) a third level of G summing modules, and (7) G output terminals. N signifies the code length and D signifies the minimum spacing of the code, E is equal to D-2, F is equal to N/D, G is the number of symbols of the data word that need to be corrected and is a natural number between 1 and E<<D.

This invention gives a coding method of MBR (Minimum Bandwidth Regenerating) codes. The related method includes the following steps: equally divide the original file of size B into k(k+1)/2 blocks, obtaining the first packets; construct a symmetrical k×k system matrix S with these first packets; generate k ID codes, wherein each ID code contains k elements; obtain the coded packet through operations between one column of the system matrix and the ID code; repeat the above steps with (n−k) different columns of the system matrix separately to get the (n−k) coded packets; construct the (n−k)×k check matrix P with the column number g which is the serial number of the ID codes in the coded packet set P.sub.g; store the rows of the system matrix and coded matrix to n nodes, each node stores one row. The present invention also involves a method to repair the failed nodes of the above coding scheme.

In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.

A turbo equalization device includes equalization circuitry, which in operation, performs an equalization process M times on an input signal, M being an integer equal to or more than 1; counter circuitry, which in operation, counts an iteration number m that indicates a number of the performed equalization process, m being an integer equal to or more than 0 and equal to less than M; control circuitry, which in operation, determines an iteration number N of a decoding process for the m times equalization processed input signal according to the iteration number m of the equalization process, the decoding process using an error correcting code that uses a belief propagation algorithm, N being an integer equal to or more than 1; and decoding circuitry, which in operation, performs a decoding process N or less times on the m times equalization processed input signal.

A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, and each data block having a number of data bits. The decoding apparatus is configured to decode, in parallel, a first codeword with one or more other codewords to determine error information associated with each codeword. For errors in a common data block shared between two codewords being decoded in parallel, the error information includes a data block identifier and associated error bit patterns. Further, the decoding apparatus is configured to update the codewords based on the error information.

An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data.

Technology is disclosed for a data storage architecture for providing enhanced storage resiliency for a data object. The data storage architecture can be implemented in a single-tier configuration and/or a multi-tier configuration. In the single-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data fragments, which are stored across many storage devices. In the multi-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data segments, which are sent to one or more tiers of storage nodes and at least one latent storage. Each of the storage nodes further encodes the data segment to generate many data fragments representing the data segment, which are stored across many storage devices associated with the storage node. The I/O operations for rebuilding the data in case of device failures is spread across many storage devices, which minimizes the wear of a given storage device.