A loss correction encoding device having an improved capability of loss correction using LDPC-CC includes a rearranging unit that rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q−1)/q of a check polynomial of the loss correction code used in a loss correction encoding unit. Specifically, the rearranging unit rearranges the information data in such a way that continuous Kmax×(q−1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit distributes the information data to information blocks from n information packets, where n satisfies the formula Kmax×(q−1)≤n.

A storage management computing device obtains an information lifecycle management (ILM) policy. A data protection scheme to be applied at a storage node computing device level is determined and a plurality of storage node computing devices are identified based on an application of the ILM policy to metadata received from one of the storage node computing devices and associated with an object ingested by the one of the storage node computing devices. The one of the storage node computing devices is instructed to generate one or more copies of the object or fragments of the object according to the data protection scheme and to distribute the object copies or one of the object fragments to one or more other of the storage node computing devices to be stored by at least the one or more other storage node computing devices on one or more disk storage devices.

This disclosure describes a programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets. This disclosure also describes techniques that include enabling data durability coding on a network. In some examples, such techniques may involve storing data in fragments across multiple fault domains in a manner that enables efficient recovery of the data using only a subset of the data. Further, this disclosure describes techniques that include applying a unified approach to implementing a variety of durability coding schemes. In some examples, such techniques may involve implementing each of a plurality of durability coding and/or erasure coding schemes using a common matrix approach, and storing, for each durability and/or erasure coding scheme, an appropriate set of matrix coefficients.

Methods and apparatus for use in a storage network operate by: storing, in a first storage unit of a first set of storage units of the storage network, a first encoded data slice corresponding to at least one data object; assigning one or more additional storage units to the storage network to form a second set of storage units, the second set of storage units including the one or more additional storage units; migrating the first encoded data slice from the first storage unit to at least one of the one or more additional storage units of the second set of storage units; and reallocating a mapping of the first encoded data slice from the first storage unit to the at least one of the one or more additional storage units of the second set of storage units.

A method includes retrieving an encoded data slice from memory of a storage network, where the encoded data slice is associated with a slice integrity value stored in the memory, and where a data segment of data is error encoded into a set of encoded data slices that includes the encoded data slice. The method further includes generating a second slice integrity value based on the retrieved encoded data slice. The method further includes determining whether the second slice integrity value compares favorably to the slice integrity value. When the second slice integrity value compares unfavorably to the slice integrity value, the method further includes facilitating rebuilding of the encoded data slice to produce a rebuilt encoded data slice. The method further includes storing the rebuilt encoded data slice in the memory.

The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.

Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.

A method begins by a processing module of a storage network receiving a first plurality of pairs of coded values corresponding to first data segments of a first data stream and a second data stream. The method continues with the processing module generating a received coded matrix to include a plurality of groups of selected coded values and when the received coded matrix includes a decode threshold number of pairs of coded values, generating a data matrix from the received coded matrix and an encoding matrix. The method continues with the processing module reproducing the first data segment of the first and second data streams, while maintaining the time alignment of the first and second data streams.

A data processing device includes an average correction processor that corrects input data based on an average value of the input data and outputs average correction data, and reversibly encodes and decodes the average value to generate a decoded average value, an irreversible encoder/decoder that encodes and decodes the average correction data and outputs first and second decoded data, a binary predictor that predicts a magnitude of a restoration error included in the second decoded data based on the first decoded data and the decoded average value and outputs a prediction result as binary data, an error estimator that outputs an estimation error based on the first decoded data, the second decoded data, and the decoded average value, and an operation circuit that outputs output data based on the second decoded data, the binary data, the estimation error, and the decoded average value.