An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

A computing device for use in a distributed storage network (DSN) to recover corrupt encoded data slices. The computing device requests, from storage units of the DSN, encoded data slices corresponding to a data segment. In response, the computing device receives at least a decode threshold number of encoded data slices and at least one integrity error message that provides an indication of a corrupt encoded data slice, such that less than a decode threshold number of valid slices is received. Utilizing at least one correction approach involving stored integrity data, the computing device corrects the corrupt slice(s) to produce a decode threshold number of encoded data slices in order to decode the corresponding data segment. A variety of correction approaches may be employed, including a multi-stage approach that utilizes data from both valid and invalid slices.

The subject technology provides for scanning blocks of a flash memory device for erased pages. A first codeword read from a page of a block in a flash memory device is received and provided to a first decoder for decoding. In response to receiving a first success indicator from the first decoder indicating that the first codeword was successfully decoded, first decoded data is provided from the first decoder to a second decoder for verification of the first decoded data. In response to receiving a first failure indicator from the second decoder indicating that the first decoded data was not verified, the page of the block is identified as being in an erased state based on the first success indicator received from the first decoder and the first failure indicator received from the second decoder.

A double factor correction Turbo decoding method based on a simulated annealing algorithm is provided, including: S1: setting an initial bit error rate P.sub.e0 and an initial solution of correction factors; S2: randomly selecting a new solution of the correction factors from a proximinal subset of a current solution, and calculating a new bit error rate P.sub.enew; S3: determining whether the new bit error rate is smaller than a bit error rate of a previous decoding, and if so, receiving the new solution of the correction factors, otherwise calculating a reception probability based on a difference between the new bit error rate and the bit error rate of the previous decoding; S4: decreasing the initial bit error rate P.sub.e0 to determine whether a termination condition is satisfied, performing S5 if the termination condition is satisfied, otherwise performing S2; and S5: outputting a current solution of the correction factors as an optimal solution.

A method of decoding a polar coded signal includes determining channel reliabilities for a plurality of polar coded bit channels in a data communication system including a plurality of frozen bit channels and non-frozen bit channels, selecting a frozen bit channel, calculating a likelihood value for a bit estimate associated with the frozen bit channel, generating a hard decision value for the bit estimate in response to the likelihood value, comparing the hard decision value for the bit estimate to a known value of a frozen bit transmitted on the frozen bit channel, in response to determining that the hard decision value for the bit estimate differs from the known value of the frozen bit transmitted on the frozen bit channel, updating an accumulated uncertainty, comparing the accumulated uncertainty to a threshold, and determining that a decoding error has occurred in response to the comparison.

A decoder performs: computing (S501) a value (i,j) of a performance-improvement metric for each kernel K.sub.i,j; and sorting (S502) the kernels in a list in decreasing order of the values (i,j). The decoder then performs a beliefs propagation iterative process as follows: updating (S503) output beliefs for the W top kernels of the list , and propagating said output beliefs as input beliefs of the neighbour kernels of said W top kernels; updating (S504) output beliefs for each neighbour kernel of said W top kernels following update of their input beliefs, and re-computing (S505) the performance-improvement metric value (i,j) for each said neighbour kernel; setting (S505) the performance-improvement metric for said W top kernels to a null value; and re-ordering (S506) the kernels in the list . Then, the decoder repeats the beliefs propagation iterative process until a stop condition is met.

Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.

Disclosed is an erasure-based Reed-Solomon code soft-decision decoding method and device, capable of reducing a decoding time while minimizing the effect on error correction performance. The Reed-Solomon code soft-decision decoding device includes an erasure control circuit configured to determine whether a number of errors in a codeword is odd or even, and to provide a key equation solver circuit with a first erasure pattern or a second erasure pattern according to a result of the determining when a decoding failure is detected by a decoding error detection circuit, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even.

Example apparatus and methods control an error correcting code (ECC) approach for data stored on a solid state device (SSD). The control may be based on a property (e.g., reliability, error state, speed) of an SSD, or on an attribute of the data to be stored. Approaches including a hybrid rateless Reed-Solomon ECC approach or a fountain code ECC approach may be selected. Example apparatus and methods may store padded portions of an ECC at different locations in an SSD. Example apparatus and methods may dynamically generate performance test data about the SSD, and dynamically control the ECC approach based on the performance test data. Different types or numbers of ECC may be produced, stored, and provided for different data sets stored at different SSDs or at different physical locations within an SSD. The SSD may be local, or may be part of a cloud-based storage system.

The present invention relates to a method of accumulating and decoding a PBCH signal received by a 5G NR receiver, the method including: generating an inversion vector for negating at least one bit of a system frame number (SFN) included the received PBCH signal; performing accumulation over at least one frame by performing modulo addition on the generated inversion vector and the received PBCH signal; decoding the accumulated PBCH signals; and checking validity of the decode PBCH and reconstructing the SFN.