Patent classifications
H03M13/37
Storage network with enhanced data access performance
A method for execution by a storage network begins by issuing a decode threshold number of read requests for a set of encoded data slices to a plurality of storage units of a set of storage units and continues by determining whether less than a decode threshold number of read requests has been received in a time window. The method continues by identifying one or more encoded data slices encoded data slices associated with read requests of the decode threshold number of read requests that have not been received and for an encoded data slice of the one or more encoded data slices, issuing a priority read request to a storage unit storing a copy of the encoded data slice. The method then continues by receiving a response from the storage unit storing the copy of the encoded data, where the storage unit storing the copy of the encoded data slice is adapted to delay one or more maintenance tasks in response to the priority read request.
Dynamic bit flipping order for iterative error correction
Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword is error corrected for a first number of iterations. The error correction includes traversing the codeword according to a first order. The codeword is error corrected for a second number of the iterations. The error correction of the codeword during a second iteration from the second number of iterations includes traversing the codeword according to a second order that is different from the first order.
Modifying storage of encoded data slices based on changing storage parameters
A method includes determining a change to storage parameters associated with storage of data objects in a storage network, where a data segment of the data objects is dispersed storage error encoded into a set of encoded data slices based on dispersed storage error encoding parameters, and where the set of encoded data slices is stored in the set of storage units. The method also includes determining a storage modification process for the set of encoded data slices based on the change to the storage parameters. The method also includes executing the storage modification process such that the set of encoded data slices are stored in the storage network in accordance with the changed storage parameters.
ITERATIVE DECODER FOR CORRECTING DRAM DEVICE FAILURES
Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.
Performing a decoding operation to simulate switching a bit of an identified set of bits of a data block
A set of bits of a segment of a memory device that is associated with an unsuccessful first decoding operation can be identified. A discrepancy value for at least one bit of the set of bits can be calculated. It can be determined whether the discrepancy value calculated for the at least one bit of the set of bits corresponds to a correction capability of the failed decoding operation. In response to determining that the discrepancy value calculated for the at least one bit corresponds to the correction capability of the failed decoding operation, the at least one bit of the set of bits can be corrected by switching a value of the at least one bit.
SYSTEMS AND METHODS OF DECODING ERROR CORRECTION CODE OF A MEMORY DEVICE WITH DYNAMIC BIT ERROR ESTIMATION
A method, of decoding error correction code of a memory device with dynamic bit error estimation, can include generating at least one metric corresponding to one or more syndromes associated with a code word, the code word comprising an error correction code of a memory device, decoding the code word by a first decoder integrated with the memory device, in response to a determination that the metric satisfies a threshold associated with the syndromes, the first decoder having a first execution property, and decoding the code word by a second decoder integrated with the memory device, in response to a determination that the metric does not satisfy the threshold associated with the syndromes, the second decoder having a second execution property distinct from the first execution property, or in response to a determination that the metric satisfies the threshold associated with the syndromes, and in response to a determination to perform further decoding.
Systems and methods for decoding error correcting codes with historical decoding information
Systems and methods are provided for decoding data read from non-volatile storage devices. A method may comprise receiving a chunk of data read from a physical location of a non-volatile storage device and searching a memory for soft information associated with the physical location using a unique identifier associated with the physical location. The soft information may be generated from one or more previous decoding processes on previous data from the physical location. The method may further comprise retrieving the soft information identified by the unique identifier associated with the physical location from the memory, decoding the chunk of data with the soft information indicating reliability of bits in the chunk of data and updating the soft information with decoding information generated during the decoding.
Increased data reliability
A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.
Memory system
In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.
Decoding device, decoding method, control circuit, and storage medium
A decoding device includes: a hard decision decoder generating a first decoding result by performing hard decision decoding of a polar code using an input signal, and generating a first error detection result by performing first error detection processing on the first decoding result; a soft decision decoder generating a second decoding result by performing successive decoding of a polar code on the input signal, obtained for each decoding step in the successive decoding, and generating a second error detection result by performing second error detection processing on a result obtained by updating the first decoding result using the second decoding result; a data selector selecting and outputting either the first decoding result or the result obtained by updating the first decoding result using the second decoding result; and a controller stopping the soft decision decoder when the data selector outputs the final decoding result.