An error correction device according to this invention includes a first correction unit configured to perform error correction decoding of data by a repetitive operation, and having a full operation state in which the repetitive operation of the error correction decoding is repeated until convergence is obtained and a save operation state in which the number of times of the repetitive operation of the error correction decoding is restricted to a predetermined number of times, an error information estimation unit configured to estimate an input error rate or an output error rate of the first correction unit using a decoding result of the first correction unit, and a control unit configured to control transition between the full operation state and the save operation state of the first correction unit based on at least one piece of information of the input error rate, the output error rate, and an operation time of the first correction unit. According to this invention, it is possible to provide an error correction device that can improve a transmission characteristic while suppressing power consumption.

A memory device includes a memory array and a memory controller. The memory array includes a first memory bank, a second memory bank, and a third memory bank. The first memory bank includes a first sub memory bank. The second memory bank includes a second sub memory bank. The memory controller, according to a write command from a host, writes first data from the host to the first memory bank and second data to the second memory bank at the same time, and writes a first Hamming weight of the first data to the third memory bank. The second data is the inverse of the first data.

A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

A hybrid quantum classical (HQC) computer system, which includes both a classical computer component and a quantum computer component, implements indirect benchmarking of a near term quantum device by directly benchmarking a virtual quantum machine that models the quantum computer device and that has a level of errors that corresponds to the level of errors associated with the quantum computer device. The direct benchmarking, conducted using quantum error correction tools, produces a probability distribution of error syndromes that may be used as a probability distribution of error syndromes for the quantum computer device.

Disclosed is a method of detecting and correcting an error in a 3D mesh model. According to the present disclosure, the method includes: determining at least one mesh on the basis of half-edge information; setting at least one cluster including the at least one mesh, on the basis of normal vector information on the at least one mesh; detecting a flip error of the at least one cluster; and correcting the at least one mesh in the at least one cluster in which the flip error is detected.

Disclosed is a method of detecting and correcting an error in a 3D mesh model. According to the present disclosure, the method includes: determining at least one mesh on the basis of half-edge information; setting at least one cluster including the at least one mesh, on the basis of normal vector information on the at least one mesh; detecting a flip error of the at least one cluster; and correcting the at least one mesh in the at least one cluster in which the flip error is detected.

The disclosure discloses an algebraic decoding method and a decoder for a (n, n(n1), n1) permutation group code in a communication modulation system. The basic principle of the decoding method is: assuming that two code elements p(r.sub.1)=s.sub.1 and p(r.sub.2)=s.sub.2 can be correctly detected in a received real vector with a length of n, including their element values s.sub.1, s.sub.2 and position indices r.sub.1, r.sub.2 in the vector, an intermediate parameter w is determined by solving an equation (r.sub.1r.sub.2)w=(s.sub.1s.sub.2)(mod n); and each code element is calculated by w according to p(i)=(s.sub.1+(nr.sub.1+i)w)(mod n), i=1, 2, . . . , n. The decoder is mainly composed of multiple n-dimensional registers, a w calculator, n code element calculators, and a code element buffer. In the disclosure, in a case where a receiver only correctly detects two code elements in a transmitted codeword with a length of n, the codeword can be correctly decoded by using the received information of the two code elements.

A memory system includes a nonvolatile memory and a memory controller. The memory controller determines a read voltage for first data encoded by a first encoding scheme, by generating a first histogram indicating the number of memory cells for each threshold voltage, and estimating the read voltage using: (a) the first histogram that is corrected based on a first parameter of the first encoding scheme, and a second parameter of a second encoding scheme, and an estimation function for estimating a read voltage for second data encoded by the second encoding scheme, or (b) the uncorrected first histogram, and the estimation function that is corrected based on the first and second parameters, or (c) the first histogram after partial correction based on the first and second parameters, and the estimation function after partial correction based on the first and second parameters.

A memory system includes a nonvolatile memory and a memory controller. The memory controller determines a read voltage for first data encoded by a first encoding scheme, by generating a first histogram indicating the number of memory cells for each threshold voltage, and estimating the read voltage using: (a) the first histogram that is corrected based on a first parameter of the first encoding scheme, and a second parameter of a second encoding scheme, and an estimation function for estimating a read voltage for second data encoded by the second encoding scheme, or (b) the uncorrected first histogram, and the estimation function that is corrected based on the first and second parameters, or (c) the first histogram after partial correction based on the first and second parameters, and the estimation function after partial correction based on the first and second parameters.