Disclosed is a method of detecting and correcting an error in a 3D mesh model. According to the present disclosure, the method includes: determining at least one mesh on the basis of half-edge information; setting at least one cluster including the at least one mesh, on the basis of normal vector information on the at least one mesh; detecting a flip error of the at least one cluster; and correcting the at least one mesh in the at least one cluster in which the flip error is detected.

A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

An error correcting method is provided, which includes the following steps. An error value is obtained. The error value is substituted into an error correcting function, so that the error correcting function causes the error value to converge to 0 in a finite time. The error correcting function conforms to a non-Lipschitzian characteristic. An embodiment of the disclosure solves the problem in traditional system stability analysis through a differential equation, adjusts parameters to determine a convergence time, and ensures that a convergence target fully conforms to an expected value and that a unique solution of the error value is 0.

An error correcting method is provided, which includes the following steps. An error value is obtained. The error value is substituted into an error correcting function, so that the error correcting function causes the error value to converge to 0 in a finite time. The error correcting function conforms to a non-Lipschitzian characteristic. An embodiment of the disclosure solves the problem in traditional system stability analysis through a differential equation, adjusts parameters to determine a convergence time, and ensures that a convergence target fully conforms to an expected value and that a unique solution of the error value is 0.

An encoding for data in an audio data stream may be indicated in the data stream using a footer stored in low-order bits of data frames in the audio data stream. When the audio data stream may include either Pulse Code Modulation (PCM) or Direct Stream Digital (DSD) data, PCM data may be marked with a footer to indicate the encoding as PCM. The footer may be a fixed value, an alternating fixed value, a predetermined sequence of values, or a value computed based on the PCM data. Examples of computed values for the footer marker may include an error code, an error correction code (ECC), and a scrambled code.

The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity.

A calculation section divides inputted data into N or M bits to calculate a first running disparity of an N or M bit data string. A determination section determines whether the data string is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated therebefore. An addition section inverts or non-inverts the data string based on a determination result by the determination section to add a flag indicating the determination result for outputting. The determination section determines not to perform inversion when the data string is a control code. The addition section adds the flag assigned to the control code. The technology is applicable to a device communicating in an SLVS-EC specification.

Systems and methods for error correction in structured light are disclosed. In one aspect, a method includes receiving, via a receiver sensor, a structured light image of at least a portion of a composite code mask encoding a plurality of codewords, the image including an invalid codeword. The method further includes detecting the invalid codeword. The method further includes generating a plurality of candidate codewords based on the invalid codeword. The method further includes selecting one of the plurality of candidate codewords to replace the invalid codeword. The method further includes generating a depth map for an image of the scene based on the selected candidate codeword. The method further includes generating a digital representation of a scene based on the depth map. The method further includes outputting the digital representation of the scene to an output device.