A writing circuit for writing write data into a memory comprises an evaluator configured for providing an error handling code on the basis of the write data. A modifier reversibly modifies extended write data comprising both the write data and the error handling code in dependence on address information related to a writing address in order to provide modified extended write data. A writer writes the modified extended write data in a position of the memory defined by a writing address. A reading circuit for reading extended read data from a memory comprises a reader configured for reading the extended read data from a position of the memory defined by a reading address. A de-modifier modifies the extended read data in dependence on address information related to a reading address in order to provide extracted read data and an extracted error handling code. An error-detector detects based on the extracted error handling code whether the extracted read data comprises an error.

A method for encoding an input data block for storage in q-level cells of solid-state memory includes producing a preliminary block from the input data block by modulation encoding at least part of the input block into a first group of q.sup.ary symbols via a first drift-tolerant encoding scheme, the preliminary block comprising the first group of q.sup.ary symbols and any remainder of the input block not encoded via the first encoding scheme; generating parity data for the preliminary block via an error-correction encoding scheme; modulation encoding the parity data and any remainder of the input block into a second group of q.sup.ary symbols via a second drift-tolerant encoding scheme; and supplying the q.sup.ary symbols of the first and second groups for storage in respective q-level memory cells.

Methods and systems for enhancing the detectability of electronic tracking messages are provided. Transmitters apply error protection encoding to the payload portion of messages to be transmitted. Transmitted messages are received by a satellite or other surveillance platform employing a compatible radio frequency receiver to collect message signals over a large area or great distance. Candidate messages are identified and the error protection encoding decoded to recover messages.

Methods and apparatus for code-based asymmetric cryptosystem using Quasi-Cyclic Moderate-Density Parity-Check (QC-MDPC) error correcting codes. Specifically, the method and apparatus generalizes the framework of (QC-MDPC) Code-Based (CB) cryptography from the binary domain (Galois Field of two elements) to an arbitrary size of Galois Field and provides an apparatus for implementing the cryptosystem with a simplified computational complexity of key generation, encryption, and decryption components of the cryptosystems and reduced sizes of the public and private security keys.

Techniques for achieving reductions in cost of encoding and decoding operations used in DNA data storage systems to facilitate reducing errors in those encoding and decoding operations while accounting for a code structure used during the encoding and decoding by constructing and using insertion-deletion-substitution (IDS) trellises for multiple traces are disclosed. A DNA sequencing channel is used to randomly sample and sequence DNA strands to generate noisy traces. Multiple trellises are independently constructed for each respective noisy trace. A forward-backward algorithm is run on each trellis to compute posterior marginal probabilities for vertices included in each trellises. An estimate of the data message sequence is then computed.

Technologies related to enhancing security of digital content are described. Linear error correction codes (LECCs) are employed for dual purposes: 1) to obfuscate digital content; and 2) to verify integrity of the digital content. A transmitter computing system obfuscates digital content based upon an obfuscation protocol, wherein the obfuscated digital content includes an LECC. A receiver computing system deobfuscates the digital content by performing the inverse of the obfuscation protocol.

Disclosed herein are embodiment that are directed to a method comprising storing each encrypted data block, of a cyphertext page, with corresponding encrypted error correction code (ECC) bits in a persistent memory device (PMD). In exemplified embodiments, the encrypted ECC bits verify both an encryption counter value of an encryption operation and a plaintext block of the cyphertext page from a decryption operation. In other embodiments, the method includes decrypting, using the decryption operation during a read operation of a memory controller, a respective one block of the cyphertext file and the corresponding encrypted ECC bits stored in the PMD using a current counter value to form the plaintext block and decrypted ECC bits. Further, the may include verifying the plaintext block with the decrypted ECC bits; and performing a security check of the encryption counter value in response to the plaintext block failing the verification, using the decrypted ECC bits. A system and secure processor that are configured to perform the disclosed methods are provided.

The present disclosure is directed to systems and methods of providing a secure quantum key distribution cryptosystem in which the quantum key data is exchanged between Alice and Bob using a quantum channel and the parity bits associated with the quantum key data are encrypted using a post-quantum computing (PQC) encryption method and communicated between Alice and Bob using a public channel.

A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.