H03M13/63

ERROR CORRECTION CODE UNIT AND ERROR CORRECTION METHOD
20190356331 · 2019-11-21 · ·

An error correction code (ECC) unit includes an error correction code (ECC) encoder configured to perform error correction code (ECC) encoding for each of a first data group and a second data group sharing at least one data with the first data group; and an error correction code (ECC) decoder configured to perform error correction code (ECC) decoding for each of the first data group and the second data group. The ECC decoder performs the ECC decoding for the second data group when the ECC decoding for the first data group fails, and does not perform the ECC decoding for the second data group when the ECC decoding for the first data group succeeds.

Encoding device, encoding method, decoding device, decoding method, and program

The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity. A calculation section divides inputted data into N or M bits to calculate a first running disparity of an N or M bit data string. A determination section determines whether the data string is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated therebefore. An addition section inverts or non-inverts the data string based on a determination result by the determination section to add a flag indicating the determination result for outputting. The determination section determines not to perform inversion when the data string is a control code. The addition section adds the flag assigned to the control code. The technology is applicable to a device communicating in an SLVS-EC specification.

Controller and memory system
11953990 · 2024-04-09 · ·

A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

TRANSMITTER AND REPETITION METHOD THEREOF

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.

POLAR CODE TRANSMISSION METHOD AND APPARATUS

Embodiments provide a Polar code transmission method and apparatus. A bit sequence is encoded into a code sequence using Polar code by a network device. The bit sequence contains a control signaling and a Cyclic Redundancy Code (CRC) sequence. The code sequence is transformed into M copies such that an i.sub.th information copy of the M copies multiples by a first matrix of the power of (i1). M is an integer and M>0. M copies of codeword was encoded by Polar code, the M copies implicitly conveys different time stamp information, which is suitable for the transmission of PBCH in 5G communication system, signaling overhead is also reduced.

Error correction method of data storage device
10439642 · 2019-10-08 · ·

An error correction code processing method includes performing a first encoding operation for a data group of a first direction; performing a second encoding operation for a data group of a second direction, wherein the data group of the first direction shares one or more data with the data group of the second direction; performing a first decoding operation of correcting an error included in the data group of the first direction; and performing a second decoding operation of correcting an error included in the data group of the second direction when the first decoding operation fails.

Transmitter and repetition method thereof

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.

SYSTEMS AND METHODS OF USING CRYPTOGRAPHIC PRIMITIVES FOR ERROR LOCATION, CORRECTION, AND DEVICE RECOVERY

The present disclosure is directed to systems and methods for the secure transmission of plaintext data blocks encrypted using a NIST standard encryption to provide a plurality of ciphertext data blocks, and using the ciphertext data blocks to generate a Galois multiplication-based authentication tag and parity information that is communicated in parallel with the ciphertext blocks and provides a mechanism for error detection, location and correction for a single ciphertext data block or a plurality of ciphertext data blocks included on a storage device. The systems and methods include encrypting a plurality of plaintext blocks to provide a plurality of ciphertext blocks. The systems and methods include generating a Galois Message Authentication Code (GMAC) authentication tag and parity information using the ciphertext blocks. The GMAC authentication tag may be encrypted to provide a GIMAC authentication tag that is communicated in parallel with the ciphertext blocks to one or more recipient systems or devices.

CACHE INDEX MAPPING
20190215021 · 2019-07-11 ·

Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.

Soft generation of biometric candidates and references based on empirical bit error probability

A biometric verification device is arranged to compare a reference hash with a verification bit string obtained from a biometric. The biometric verification device includes a candidate bit string generator arranged to generate candidate bit strings from the verification bit string and error probabilities; a hash unit arranged to apply a cryptographic hash function to the generated candidate bit strings to obtain candidate hashes; and a comparison unit arranged to verify if a candidate hash generated by the hash unit matches a reference hash.