The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity.

A calculation section divides inputted data into N or M bits to calculate a first running disparity of an N or M bit data string. A determination section determines whether the data string is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated therebefore. An addition section inverts or non-inverts the data string based on a determination result by the determination section to add a flag indicating the determination result for outputting. The determination section determines not to perform inversion when the data string is a control code. The addition section adds the flag assigned to the control code. The technology is applicable to a device communicating in an SLVS-EC specification.

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.

An error correction code processing method includes performing a first encoding operation for a data group of a first direction; performing a second encoding operation for a data group of a second direction, wherein the data group of the first direction shares one or more data with the data group of the second direction; performing a first decoding operation of correcting an error included in the data group of the first direction; and performing a second decoding operation of correcting an error included in the data group of the second direction when the first decoding operation fails.

A transceiver architectures can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on concatenations of an E8 lattice having binary and non-binary codes. The data can be transmitted at a high speed according to the constellation with an embedded E8 lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency with a high spectral efficiency.

Multi-reliability regenerating (MRR) erasure codes are disclosed. The erasure codes can be used to encode and regenerate data. In particular, the regenerating erasure codes can be used to encode data included in at least one of two or more data messages to satisfy respective reliability requirements for the data. Encoded portions of data from one data message can be mixed with encoded or unencoded portions of data from a second data message and stored at a distributed storage system. This approach can be used to improve efficiency and performance of data storage and recovery in the event of failures of one or more nodes of a distributed storage system.

The present disclosure provides a method and a device for transmitting data using a LDPC code. The method for transmitting data using a LDPC code includes: determining a check code length according to a current LDPC code rate; informing a receiving end about the current LDPC code rate and the check code length, adding a check code with the check code length to data to be sent, and implementing a LDPC encoding using the current LDPC code rate, so as to obtain LDPC code data; and sending the LDPC code data to a receiving end. The method and the device of the present disclosure can improve spectrum effectiveness of transmitting data using LDPC code.

In a general aspect, a key encapsulation mechanism is used in a communication network. In some aspects, an error vector derivation function is applied to a random value to produce an error vector, and a plaintext value is obtained based on the random value. The error vector and the plaintext value are used in an encryption function to produce a ciphertext, and a key derivation function (KDF) is applied to the random value to produce a key derivation function output that includes a symmetric key and a confirmation value. The symmetric key is used to generate an encrypted message based on an unencrypted message. The ciphertext, the confirmation value, and the encrypted message are provided for transmission in a communication network.

Data is received from a physical coding sublayer (PCS) of a physical layer, where the physical layer comprises a BASE-R physical layer. The data is used to generate a forward error correction (FEC) block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block. The FEC block is scrambled using a pseudo-noise sequence. The FEC block is sent to a physical medium attachment (PMA) sublayer of the physical layer.

One aspect of the present disclosure relates to a conversion device including an acquisition unit configured to acquire a first bit string having a first bit length L1; a conversion unit configured to convert, in accordance with conversion information that associates respective bit strings each having the first bit length L1 with bit strings each having a second bit length L2 uniquely assigned to the respective bit strings, the first bit string into a second bit string having the second bit length L2. The conversion information is created by searching for a clique that includes 2.sup.L1 or more nodes, from a graph including nodes and an edge representing the bit strings each having the second bit length L2 that satisfy a predetermined constraint condition.

Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.