Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die in a first layer; an interposer in a second layer not coplanar with the first layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the interposer coupling the first IC die and a second IC die. The first IC die is configured to transmit at a first supply voltage through the first conductive pathway to a second IC die, the second IC die is configured to transmit to the first IC die through the second conductive pathway at a second supply voltage simultaneously with the first die transmitting at the first supply voltage, and the first supply voltage is different from the second supply voltage.

A high speed but power-efficient electronic communications protocol may comprise dual simplex links, each operating in a differential high-speed mode and each capable of a low-speed signaling mode. When both links operate in high speed mode, signaling is performed in-band, with signals embedded as metadata attached to transmitted packets. When one of the links is put into a low-power mode, the return-path signaling may be performed on the two wires previously used for high-speed transmissions. One wire may be used for flow control or other signaling, while the other wire may be used for a wake command, which may initiate the low-power mode to be elevated to a high-speed mode. Multiple lanes may be organized to operate in parallel for each link, allowing for a very high speed communications protocol that may be easily switched into and out of a low-power state without additional sideband wiring.

A high speed but power-efficient electronic communications protocol may comprise dual simplex links, each operating in a differential high-speed mode and each capable of a low-speed signaling mode. When both links operate in high speed mode, signaling is performed in-band, with signals embedded as metadata attached to transmitted packets. When one of the links is put into a low-power mode, the return-path signaling may be performed on the two wires previously used for high-speed transmissions. One wire may be used for flow control or other signaling, while the other wire may be used for a wake command, which may initiate the low-power mode to be elevated to a high-speed mode. Multiple lanes may be organized to operate in parallel for each link, allowing for a very high speed communications protocol that may be easily switched into and out of a low-power state without additional sideband wiring.

An apparatus for detecting Packet Energy Transfer (PET) in a cable is disclosed herein. The PET detecting apparatus includes an input adapted to generate a current by operative communication of the input with the cable, wherein the cable communicates PET as a pulse train. A spectral analyzer compares frequencies of maxima of the power spectrum of a signal derived from the current with a fundamental frequency of the pulse train and a harmonic frequency of the pulse train to detect PET in the cable. A power maximum of the power spectrum at the fundamental frequency and a second power maximum of the power spectrum at the harmonic frequency indicates PET in the cable. No power maximum of the power spectrum at the fundamental frequency or no second power maximum of the power spectrum at the harmonic frequency indicates no PET in the cable.

An apparatus for detecting Packet Energy Transfer (PET) in a cable is disclosed herein. The PET detecting apparatus includes an input adapted to generate a current by operative communication of the input with the cable, wherein the cable communicates PET as a pulse train. A spectral analyzer compares frequencies of maxima of the power spectrum of a signal derived from the current with a fundamental frequency of the pulse train and a harmonic frequency of the pulse train to detect PET in the cable. A power maximum of the power spectrum at the fundamental frequency and a second power maximum of the power spectrum at the harmonic frequency indicates PET in the cable. No power maximum of the power spectrum at the fundamental frequency or no second power maximum of the power spectrum at the harmonic frequency indicates no PET in the cable.

A slave communication apparatus including a clock recovering section that recovers a clock signal from a transmission signal having a first signal value when the clock is a first level, a second signal value when the clock is a second level and data has a first data value, and a third signal value between the first and second signal values when the clock is the second level and the data has a second data value; and a data recovering section that recovers the data, wherein the data recovering section sets the data threshold value to be a first setting value between the second and third signal values in response to the recovered data having the second data value, and sets the data threshold value to be a second setting value between the first and third signal values in response to the recovered data having the first data value.

A communication system according to an embodiment of the present disclosure is a communication system that transmits a signal from a plurality of transmission devices to one reception device via a transmission path. In the communication system, the transmission path includes a branch point at a midpoint, includes a plurality of first signal lines that couples the transmission devices and the branch point to each other, and further includes a second signal line that couples the branch point and the reception device to each other. Of the plurality of first signal lines or the second signal line, at least the plurality of first signal lines has a resistor element in proximity to the branch point.

A communication system according to an embodiment of the present disclosure is a communication system that transmits a signal from a plurality of transmission devices to one reception device via a transmission path. In the communication system, the transmission path includes a branch point at a midpoint, includes a plurality of first signal lines that couples the transmission devices and the branch point to each other, and further includes a second signal line that couples the branch point and the reception device to each other. Of the plurality of first signal lines or the second signal line, at least the plurality of first signal lines has a resistor element in proximity to the branch point.

A reception-side IC chip (1a) includes a pad (15) which is connected to a transmission line (2) which is outside the chip and has a characteristic impedance Z0 of 50Ω, a signal line (16), one end of which is connected to the pad (15), a reception-side input unit circuit (10) configured to receive a signal (S) transmitted from a transmission-side IC chip via the transmission line (2), a 50-Ω termination resistor (11), for impedance matching, which is connected between a predetermined voltage and the other end of the signal line (16) and is configured to terminate the transmission line (2), and a capacitor (12) inserted between a node (A) of the signal line (16) and the termination resistor (11) and an input terminal (In) of the reception-side input unit circuit (10). A DC-blocking circuit is formed by the capacitor (12).

Binary data is processed through a differential pre-encoder, which includes a simple modulo-2 addition. This step is used to cancel the propagation error that can be introduced by duo-binary modulation and to simplify demodulation. Next the duo-binary encoder introduces controlled Inter Symbol Interference between a previously sent bit and a present bit to compress the spectral density closer to the DC. Next a 60-GHz carrier is modulated and transmitted over differential transmission lines.