An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Precompensator-based quantization techniques offer a way to reduce the complexity and power requirements of clock recovery modules while offering improved timing recovery performance relative to a bang-bang scheme operating in a lossy channel. One illustrative method embodiment includes: (a) obtaining a receive signal having a sequence of symbols from a symbol set, the receive signal exhibiting trailing intersymbol interference; (b) operating on the receive signal with a precompensation unit having a set of comparators to produce, for each sampling instant, a set of comparator results representing a quantized receive signal value, the set of comparators applying a set of threshold values that at least partly compensate for the trailing intersymbol interference; (c) deriving a symbol decision from each set of comparator results; (d) combining the symbol decisions with said quantized receive signal values to determine an estimated timing error for each sampling instant; and (e) filtering the estimated timing errors to generate a sampling clock.

Mechanisms to reduce noise and/or energy consumption in PAM communication systems, utilizing conditional symbol substitution in each burst interval of a multi-data lane serial data bus.

Aspects of the subject disclosure may include, for example, a node device includes an interface configured to receive first signals. A plurality of coupling devices are configured to launch the first signals on a transmission medium as a plurality of first guided electromagnetic waves at corresponding plurality of non-optical carrier frequencies, wherein the plurality of first guided electromagnetic waves are bound to a physical structure of the transmission medium. Other embodiments are disclosed.

Aspects of the subject disclosure may include, for example, a node device includes an interface configured to receive first signals. A plurality of coupling devices are configured to launch the first signals on a transmission medium as a plurality of first guided electromagnetic waves at corresponding plurality of non-optical carrier frequencies, wherein the plurality of first guided electromagnetic waves are bound to a physical structure of the transmission medium. Other embodiments are disclosed.

The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

The continuous demand for capacity and the limited available spectrum in wireless and wired communication has led to reliance on advanced modulation techniques to dramatically increase the number of bits per hertz per second. This demand in capacity and using the higher order constellations shorten the link range, and as a result, system gain becomes an important characteristic. The modulation techniques described here improve the system gain by, e.g., as much as 2.5 dB in high order modulations such as 4096-QAM. The modulation techniques include reducing the peak to average ratio and adding shaping gain. These techniques dramatically improve the system capacity, system gain, power consumption and system cost.

The continuous demand for capacity and the limited available spectrum in wireless and wired communication has led to reliance on advanced modulation techniques to dramatically increase the number of bits per hertz per second. This demand in capacity and using the higher order constellations shorten the link range, and as a result, system gain becomes an important characteristic. The modulation techniques described here improve the system gain by, e.g., as much as 2.5 dB in high order modulations such as 4096-QAM. The modulation techniques include reducing the peak to average ratio and adding shaping gain. These techniques dramatically improve the system capacity, system gain, power consumption and system cost.

The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.