A transmitter includes: a pulse amplitude modulation encoder that encodes serial data to multi-bit transmission data of a first data group and a second data group; a first driver that converts first multi-bit transmission data of the first data group to a first differential signal having a first voltage swing width; a second driver that converts second multi-bit transmission data of the second data group to a second differential signal having a second voltage swing width narrower than the first voltage swing width; a first voltage regulator that provides to the second driver a first low swing voltage for generating the second differential signal; a second voltage regulator that provides to the second driver a second low swing voltage less than the first low swing voltage; and a constant current load switch that provides a current path between the first and second voltage regulators depending on deactivation of the second driver.

A methodology for capturing analog information, such as from an analog sensor, including converting the analog information to a train of pulses, representing the analog information as the number of pulses in the pulse train. This pulse count data can be communicated to a processor configured to count the pulses in the pulse train, and convert this pulse count data into digital data corresponding to the analog information. An example embodiment uses a DAC/comparator to convert the analog information (such as a sensor reading) into a pulse train derived from a DAC count (such as can be generated by a DAC counter from an input DAC clock) that is compared with an analog magnitude (analog information), such that the DAC count, which can be represented by a number of DAC clock pulses, provides the pulse train (pulse count data) that corresponds to the analog information.

A methodology for capturing analog information, such as from an analog sensor, including converting the analog information to a train of pulses, representing the analog information as the number of pulses in the pulse train. This pulse count data can be communicated to a processor configured to count the pulses in the pulse train, and convert this pulse count data into digital data corresponding to the analog information. An example embodiment uses a DAC/comparator to convert the analog information (such as a sensor reading) into a pulse train derived from a DAC count (such as can be generated by a DAC counter from an input DAC clock) that is compared with an analog magnitude (analog information), such that the DAC count, which can be represented by a number of DAC clock pulses, provides the pulse train (pulse count data) that corresponds to the analog information.

Techniques facilitating reduction and/or mitigation of crosstalk in quantum bit gates of a quantum computing circuit are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a signal generation component that implements a control sequence that comprises a single pulse type for a first quantum bit and at least a second quantum bit of a quantum circuit. The computer-executable components can also comprise a coordination component that synchronizes a first pulse of a first channel of the first quantum bit and at least a second pulse of at least a second channel of the second quantum bit. The coordination component can simultaneously apply the first pulse to the first quantum bit and at least the second pulse to at least the second quantum bit.

The continuous demand for capacity and the limited available spectrum in wireless and wired communication has led to reliance on advanced modulation techniques to dramatically increase the number of bits per hertz per second. This demand in capacity and using the higher order constellations shorten the link range, and as a result, system gain becomes an important characteristic. The modulation techniques described here improve the system gain by, e.g., as much as 2.5 dB in high order modulations such as 4096-QAM. The modulation techniques include reducing the peak to average ratio and adding shaping gain. These techniques dramatically improve the system capacity, system gain, power consumption and system cost.

The continuous demand for capacity and the limited available spectrum in wireless and wired communication has led to reliance on advanced modulation techniques to dramatically increase the number of bits per hertz per second. This demand in capacity and using the higher order constellations shorten the link range, and as a result, system gain becomes an important characteristic. The modulation techniques described here improve the system gain by, e.g., as much as 2.5 dB in high order modulations such as 4096-QAM. The modulation techniques include reducing the peak to average ratio and adding shaping gain. These techniques dramatically improve the system capacity, system gain, power consumption and system cost.

The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Some embodiments include apparatus and methods using an input node, an analog to digital converter (ADC) including an input coupled to the input node, a first feedforward equalizer (FFE) including an input coupled to an output of the ADC, a second FFE including an input coupled to the output of the ADC, and a decision feedback equalizer (DFE) including a first input, a second input, and an output, the first input coupled to an output of the first FFE, and the second input coupled to an output of the second FFE.

The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

An apparatus includes a transmitter circuit coupled to a termination resistor. The transmitter circuit generates a number of link pulses. A driver circuit is coupled to the transmitter circuit to control a dynamic range of the link pulses. A transformer couples the termination resistor via a transmission medium to a far-end transceiver. The driver circuit controls the dynamic range of the link pulses by providing complementary digital input signals to the transmitter circuit, and the complementary digital input signals include ramp sections.