Aspects of the subject disclosure may include, for example, a node device includes an interface configured to receive first signals. A plurality of coupling devices are configured to launch the first signals on a transmission medium as a plurality of first guided electromagnetic waves at corresponding plurality of non-optical carrier frequencies, wherein the plurality of first guided electromagnetic waves are bound to a physical structure of the transmission medium. Other embodiments are disclosed.

Aspects of the subject disclosure may include, for example, a node device includes an interface configured to receive first signals. A plurality of coupling devices are configured to launch the first signals on a transmission medium as a plurality of first guided electromagnetic waves at corresponding plurality of non-optical carrier frequencies, wherein the plurality of first guided electromagnetic waves are bound to a physical structure of the transmission medium. Other embodiments are disclosed.

A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.

Techniques facilitating reduction and/or mitigation of crosstalk in quantum bit gates of a quantum computing circuit are provided. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a signal generation component that implements a control sequence that comprises a single pulse type for a first quantum bit and at least a second quantum bit of a quantum circuit. The computer-executable components can also comprise a coordination component that synchronizes a first pulse of a first channel of the first quantum bit and at least a second pulse of at least a second channel of the second quantum bit. The coordination component can simultaneously apply the first pulse to the first quantum bit and at least the second pulse to at least the second quantum bit.

Communication systems are described that use signal constellations, which have unequally spaced (i.e. geometrically shaped) points. In many embodiments, the communication systems use specific geometric constellations that are capacity optimized at a specific SNR. In addition, ranges within which the constellation points of a capacity optimized constellation can be perturbed and are still likely to achieve a given percentage of the optimal capacity increase compared to a constellation that maximizes d.sub.min, are also described. Capacity measures that are used in the selection of the location of constellation points include, but are not limited to, parallel decode (PD) capacity and joint capacity.

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.