Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more of the subgroups, a TDM transmitter circuit is connected to a TDM receiver circuit through a selected interconnect, the drivers of the nets of the subgroup are connected to the TDM transmitter circuit, and loads of the nets of the subgroup are connected to the TDM receiver circuit.

Systems and methods for reducing phase delay variation impact are described. A microcontroller can receive a sequence of phase offsets determined by a slave device over time. The microcontroller can determine a weight vector based on a metric associated with the sequence of phase offsets. The microcontroller can adjust a set of filter coefficients based on the weight vector. The set of filter coefficients can be filter coefficients of a filter being implemented by the slave device to filter incoming packet data.

Systems and methods for reducing phase delay variation impact are described. A microcontroller can receive a sequence of phase offsets determined by a slave device over time. The microcontroller can determine a weight vector based on a metric associated with the sequence of phase offsets. The microcontroller can adjust a set of filter coefficients based on the weight vector. The set of filter coefficients can be filter coefficients of a filter being implemented by the slave device to filter incoming packet data.

Provided is a digital switch including: a plurality of input-side memories, which are arranged in a one-to-one correspondence with a plurality of input ports, and are configured to accumulate time-division multiplexed data; a plurality of output-side memories, which are arranged in a one-to-one correspondence with a plurality of output ports, and are configured to accumulate time-division multiplexed data; and a switch matrix configured to receive, as input, the time-division multiplexed data read out in every cycle from each of the plurality of input-side memories, and execute routing for selecting, in accordance with a connection control signal received from outside, any one of the plurality of output-side memories such that the time-division multiplexed data read out in every cycle is output from each of the plurality of output ports without causing a difference in delay, to output the time-division multiplexed data.

Provided is a digital switch including: a plurality of input-side memories, which are arranged in a one-to-one correspondence with a plurality of input ports, and are configured to accumulate time-division multiplexed data; a plurality of output-side memories, which are arranged in a one-to-one correspondence with a plurality of output ports, and are configured to accumulate time-division multiplexed data; and a switch matrix configured to receive, as input, the time-division multiplexed data read out in every cycle from each of the plurality of input-side memories, and execute routing for selecting, in accordance with a connection control signal received from outside, any one of the plurality of output-side memories such that the time-division multiplexed data read out in every cycle is output from each of the plurality of output ports without causing a difference in delay, to output the time-division multiplexed data.

A multiplexer device that is operable to generate from one or more input channels a multiplexed output signal. When generating the multiplexed output signal the multiplexing circuit is configured to encode the measurement values for the plurality of input channels from which input signals were provided to the multiplexer device into the multiplexed output signal in such a manner that respective measurement values from different ones of the plurality of input channels can be identified directly from the multiplexed output signal.

A multiplexer device that is operable to generate from one or more input channels a multiplexed output signal. When generating the multiplexed output signal the multiplexing circuit is configured to encode the measurement values for the plurality of input channels from which input signals were provided to the multiplexer device into the multiplexed output signal in such a manner that respective measurement values from different ones of the plurality of input channels can be identified directly from the multiplexed output signal.

A serializer includes a recursive tree of serializer unit cells. Each serializer unit cell includes a multiplexer and a plurality of flip-flops coupled to the multiplexer. Each serializer unit cell contains a state machine defining operation of the corresponding serializer unit cell. The recursive tree is organized with upper level serializer unit cells disposed more closely to a serializer output than are lower level serializer unit cells. The recursive tree is configured such that each serializer unit cell that is adjacent to and in an upper position relative to a corresponding lower level serializer unit cell directs the corresponding lower level serializer unit cell to output data, and the corresponding lower level serializer unit cell communicates to the corresponding serializer unit cell when the corresponding lower level serializer unit cell is done outputting data.

A serializer includes a recursive tree of serializer unit cells. Each serializer unit cell includes a multiplexer and a plurality of flip-flops coupled to the multiplexer. Each serializer unit cell contains a state machine defining operation of the corresponding serializer unit cell. The recursive tree is organized with upper level serializer unit cells disposed more closely to a serializer output than are lower level serializer unit cells. The recursive tree is configured such that each serializer unit cell that is adjacent to and in an upper position relative to a corresponding lower level serializer unit cell directs the corresponding lower level serializer unit cell to output data, and the corresponding lower level serializer unit cell communicates to the corresponding serializer unit cell when the corresponding lower level serializer unit cell is done outputting data.

Techniques for facilitating a robust clock synchronization across a computer network that presumes network jitter exists are discussed herein. A first device and a second device transceive a plurality of sets of time-synchronization messages to synchronize a synchronization clock of the second device to a first clock of the first device. The second device calculates a smoothing of time delay data of a plurality of sets. The time delay data is associated with a transmission duration of time-synchronization messages of the sets of the plurality. The second device sets a synchronization clock based on a time at the first device and the smoothed time delay data.