Patent classifications
H04L1/24
INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING DEVICE
This information processing system inputs/outputs data normally, even when a serial communication bus is extended by network communication. The information processing system is provided with: a device; a device control unit for controlling the device; a device interface unit which interfaces with the device control unit; an information processing device provided with an application interface unit which interfaces with an application; a channel establishment unit which connects, via a communication unit, the application interface unit and the device interface unit, and establishes a control channel and a data channel between the application and the device; and an error suppression unit which suppresses the occurrence of error in data transfer over the channel established by the channel establishment unit.
NFMI BASED ROBUSTNESS
One example discloses an apparatus for near-field magnetic induction (NFMI) based robustness, including: a first wireless device including a first wireless signal interface and a first NFMI signal interface; wherein the first wireless signal interface is configured to receive a data set from a third wireless device; wherein the first NFMI signal interface is configured to communicate with a second wireless device through a second NFMI signal interface; and wherein the first wireless device is configured to detect an error in the data set received from the third wireless device and in response to detecting the error configure the first NFMI signal interface to receive the data set from the second wireless device through the second NFMI signal interface.
Multi-wire symbol transition clocking symbol error correction
Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.
Emulation and debug interfaces for testing an integrated circuit with an asynchronous microcontroller
A method of testing a data transmission and reception system comprises sending a test signal from a transmitter (14) of the system to a receiver (12) of the system, and analyzing the received signal. A duty cycle relationship is varied between the test signal and the timing signal used by the receiver of the system, and the effect of the duty cycle variation is analyzed. Varying the duty cycle relationship provides duty cycle distortion (DCD), and this can be considered as a form of embedded jitter insertion. This type of jitter can be measured relatively easily.
Throughput test method and apparatus
Disclosed are a throughput test method and apparatus. The method includes: a first network device generating a periodic detection message through a data processor; the first network device sending the detection message to a second network device to be tested, wherein a first throughput value of the first network device is greater than or equal to a second throughput value of the second network device; the first network device receiving a loopback detection message looped back by the second network device; the first network device obtaining a first quantity value of the detection messages as well as a second quantity value of the loopback detection messages; and the first network device obtaining the second throughput value characterizing the throughput of the second network device through the data processor based on the first quantity value and the second quantity value.
Transmitter noise in system budget
One embodiment provides an apparatus. The example apparatus includes a root mean square (RMS) distortion determination module configured to determine an RMS distortion error and a signal to noise and distortion ratio (SNDR), the RMS distortion error determined based, at least in part, on a portion of a transmitted pulse centered at or near a transmitted pulse maximum amplitude and the SNDR determined based, at least in part, on the RMS distortion error.
Anomaly detection through header field entropy
An approach for detecting anomalous flows in a network using header field entropy. This can be useful in detecting anomalous or malicious traffic that may attempt to “hide” or inject itself into legitimate flows. A malicious endpoint might attempt to send a control message in underutilized header fields or might try to inject illegitimate data into a legitimate flow. These illegitimate flows will likely demonstrate header field entropy that is higher than legitimate flows. Detecting anomalous flows using header field entropy can help detect malicious endpoints.
System and method for testing filters in redundant signal paths
A system and method for detecting a failure in a redundant signal path during operation of the redundant path is disclosed. A test signal is sequentially injected into each signal path while an input signal is conducted by the other signal path not receiving the test signal. The test signal is selected at a frequency to verify operation of a filter connected in series along each path. A processor generates the test signal, injects the test signal at the input of the filter, and receives the output of the filter. The processor then generates a frequency response of the filter in each signal path as a function of the output from the filter and of the original test signal. The frequency response obtained along each of the redundant signal paths is compared to each other to detect a failure of one of the filters present along the respective signal paths.
System and method for testing filters in redundant signal paths
A system and method for detecting a failure in a redundant signal path during operation of the redundant path is disclosed. A test signal is sequentially injected into each signal path while an input signal is conducted by the other signal path not receiving the test signal. The test signal is selected at a frequency to verify operation of a filter connected in series along each path. A processor generates the test signal, injects the test signal at the input of the filter, and receives the output of the filter. The processor then generates a frequency response of the filter in each signal path as a function of the output from the filter and of the original test signal. The frequency response obtained along each of the redundant signal paths is compared to each other to detect a failure of one of the filters present along the respective signal paths.
METHOD AND DEVICE FOR CONTROLLING A VECTOR PROCESSOR
In accordance with an embodiment the method includes temporarily configuring the vector processor with a new set of vectoring coefficients during one or more selected symbol positions; restoring the current set of vectoring coefficients outside the one or more selected symbol positions; obtaining at least one error measure over respectively at least one line of the group of vectored lines during the one or more selected symbol positions; and determining a suitability indication for the new set of vectoring coefficients based on the obtained at least one error measure.