Introduced here are techniques for implementing a clock and data recovery circuit with improved tendencies, such a pull up and/or pull down tendencies. In various embodiments, the CDR circuit includes a phase detector that receives an input signal and a output reference clock signal. The phase detector then outputs two signals to charge pump. The output from the charge pump drives an oscillator control voltage up or down depending the current from the charge pump. A lock detector detects whether a lock has occurred by comparing the oscillator control voltage to a predetermined threshold voltage. A lock can occur when the circuit has settled into a frequency substantially near the frequency of the input signal and the oscillator control voltage is substantially near the threshold voltage. A controller circuit can control a sweeping of an available frequency range by the circuit until a lock occurs.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A method and system implements a repeater in a link of a communication medium. The method and system enables a counter to count alternations of a clock signal received from a host or device over the link, compares a value of the counter to a reference count, adjusts a frequency selection based on the comparison of the value of the counter to the reference count, and locks the frequency selection in response to the counter matching the reference count.

A circuit includes a phase and frequency detector circuit to generate a first phase detect signal indicative of whether a polarity of a first clock is the same as a polarity of a second clock upon occurrence of an edge of a data signal. The second clock being 90 degrees out of phase with respect to the first clock. A lock detect circuit determines, based on the first phase detect signal, that a third clock is one of frequency and phase locked to the data signal, frequency and quadrature locked to the data signal, and not frequency locked to the data signal.

Apparatus and associated methods relate to implementing an analog auxiliary clock and data recovery (CDR) path to provide a high bandwidth CDR in a transceiver that supports both PAM4 and NRZ signaling. In an illustrative example, the auxiliary CDR path may include a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL. When the PFD-based PLL is locked to a reference clock signal of the transceiver, the PFD-based PLL may be then disabled and the PD-based PLL may be then enabled. Implementing the auxiliary CDR path may advantageously enable the transceiver to implement much larger parts per million (ppm) acquisition and tracking, and thus enable the transceiver to advantageously support new standards such as Peripheral Component Interconnect Express (PCIe) 5.0 and PCIe 6.0, for example.

Provided are an initial access method and apparatus of a wireless communication system. The initial access method of a terminal in a wireless communication system includes: detecting at least one synchronization signal included in a plurality of synchronization signal blocks; selecting at least one synchronization signal among the detected at least one synchronization signal; and performing an initial access procedure based on the selected at least one synchronization signal.

A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2.sup.N1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

The present disclosure relates to registration methods and devices. One example method includes obtaining, by a line card, line card information of the line card, the line card comprising a fabric interface chip optically interconnected to a switch fabric chip in at least one switch fabric card by using an optical fiber, and sending, by the line card, the line card information to the at least one switch fabric card through an optical interconnect path. The at least one switch fabric card registers the line card based on the line card information.

The present technology relates to a reception apparatus and a data processing method that enable clock synchronization in a more suitable manner. The reception apparatus receives a digital broadcast signal of an IP transmission method that includes time information and a stream of content. The time information includes a seconds field and a nanoseconds field. The reception apparatus then generates a processing clock synchronized with the time information on the basis of the time information included in the digital broadcast signal, and processes the stream included in the digital broadcast signal on the basis of the processing clock. The present technology can be applied to, for example, television receivers conforming to the IP transmission method.

Provided is a computation device including a communication interface; a first transmission control part for sending a first communication frame at every predetermined cycle via a transmission path; a second transmission control part for sending a second communication frame in response to an arbitrary event request; and a priority management part. Upon receiving an issuance request of a second event request from a second event issuance part, the priority management part waits for completion of sending processing for a second communication frame corresponding to a first event request currently processed by the second transmission control part, and permits issuance of the second event request to the second event issuance part. The second transmission control part suspends processing for a subsequent first event request following the first event request currently processed until completion of processing for the second event request is complete.