A time synchronization method, a time synchronization sender, a time synchronization receiver and a time synchronization system are provided. The method includes: determining whether at least one parameter causing recalculation of a best master clock (BMC) algorithm changes; in a case where it is determined that the parameter changes, sending a 1588 standard-based Announce message; and in a case where it is determined that the parameter does not change, sending a keep-alive message of the Announce message. In the present disclosure, by distinguishing keep-alive messages from protocol messages, the problem that a CPU system is busy due to the processing of Announce messages is solved, thereby realizing the optimization of the 1588 protocol, and reducing the impact on the CPU.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

A system for enabling data syncing between a host device and an electronic device includes a first port configured to be coupled to a first electronic device, a second port configured to be coupled to the host device, and a data sync switch coupled to the first port and the second port. The data sync switch is switchable between a first state, in which data communication between the electronic device and the host device is enabled, and a second state, in which data communication between the electronic device and the host device is disabled. The system also includes an authorization device configured to couple to an authorizing physical object and generate an output signal. The data sync switch is in one of the first state and the second state based on the output signal from the authorization device.

There is a communications network node comprising a transmitter or a receiver configured to communicate with a plurality of other nodes via an interconnection medium interconnecting the node and the other nodes. The node is frequency synchronized with regard to signal transmission or reception, via a frequency synchronization mechanism, with at least one of the other nodes. The node has at least one store holding phase data relating to an amount of phase asynchrony and path characteristics between the node and at least one of the other nodes. A phase controller uses the stored data to adjust phase used by the node such that the recovery of data when communicating with at least one other node is facilitated.

A signal recovery circuit includes an oscillator that generates a first clock of which a frequency is variable, and a feedback circuit that controls the oscillator to synchronize the first clock with input data, depending on a phase relationship between the input data and the first clock, the feedback circuit including a control portion that controls the oscillator depending on the phase relationship between the input data and the first clock, a first phase detection circuit that generates a clock phase control signal depending on the phase relationship between the input data and the first clock, an output data generation circuit that generates output data by latching the input data at a change edge of the first clock, and a lock detection circuit that outputs a lock detection signal indicating whether a state is a lock state or a non-lock state.

Phase detectors for clock and data recovery circuits are provided herein. In certain implementations, a phase detector includes sampling circuitry that generates a plurality of samples of an input data signal based on timing of a plurality of clock signals, a binary response circuit that processes the plurality of samples to generate a plurality of binary output signals providing a binary detector response, and a linear response circuit that processes the plurality of samples to generate a plurality of linear output signals providing a linear detector response. The phase detector generates one or more data output signals based on the plurality of samples to thereby recover data from the input data signal.

A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

A method includes (a) receiving from several different storage systems, several discovery packets, each different type of system having a different minimal amount of configuration information required to initialize, (b) displaying an identifier for each system from which a discovery packet was received, (c) receiving a selection of a particular system, (d) determining which type of system the selected system is, each type being associated with a distinct set of initialization parameter selection choices reflecting the minimal amount of configuration information required to initialize a system of that type, (e) displaying the initialization parameter selection choices associated with the determined type of system, (f) receiving initialization parameter selections responsive to the displayed initialization parameter selection choices, and (g) sending an initialization command to the selected particular system including the received initialization parameter selections to allow the selected particular system to be properly initialized.