System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the FAW in the incoming data, with each comparator configured to serially compare multiple windows of a parallel M-bit block (as provided from a parallel data bus) with the FAW. Multiple comparators in the framer may operate in parallel to search for the FAW at different windows. This configuration can significantly reduce the comparator count and so the gate count as well as the chip area in a framer. Power consumption can be advantageously reduced as one comparator operating serially consumes less power than multiple comparators in parallel because less gate toggling is involved.

A receiver for processing a data stream includes: a bursty phase detector having a first voltage-controlled oscillator configured to provide a first VCO phase, a signal stream detector configured to provide a data stream phase and a data stream detect signal, and a delay component configured to receive the data stream; a clocking circuit coupled to receive an output of the delay component, the data stream phase, and the data stream detect signal, the clocking circuit configured to provide a second VCO phase at an output of the clocking circuit, wherein the clocking circuit is configured to operate based on a fractional relationship between a reference clock frequency and an output frequency; and a data sample selector with a first input coupled to the output of the delay component, and a second input coupled to the output of the clocking circuit.

Prior to joining a device to a network, the device is connected to an external system via a local connection. The external system provides the device with a local time stamp that includes a local time value and a local time error value. The device may use the time information to communicate with the external system. After the device is joined to the network, the device may transmit a communication on the network that includes time information. If so, then the communication includes a time value based on the device's time value and a time error value set to a value indicating a maximum error. The network is protected from potentially poor quality time information. Any device that receives the communication rejects the time information since the time error value indicates a maximum error.

A method for measuring one-way delays in a communications network, the method comprising: maintaining, at a third node having a reference clock, a first virtual clock state emulating a first node clock located at a first node and a second virtual clock state emulating a second node clock located at a second node; registering a timeset comprising transmission and reception times at the first node and the second node, respectively, for each packet of a plurality of packets that are transmitted from the first node to the second node and reflected from the second node back to the first node; converting times in the timeset, responsive to the first and/or second virtual clocks, into times in accordance with the reference clock; calculating, for each packet of the plurality of packets, a forward one-way delay (FOWD) and a reverse one-way delay (ROWD), responsive to the converted timeset.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method for calibrating a clock recovery circuit includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where each pair of symbols includes a first symbol and a second symbol, generating a second clock signal by delaying the first clock signal by a first delay value, generating a third clock signal by delaying the second clock signal, calibrating the second clock signal and the third clock signal by initializing the first delay value such that the first sampling circuit, the second sampling circuit and the third sampling circuit capture the same symbol in a first pair of symbols, and incrementally increasing the first delay value until the second sampling circuit and the third sampling circuit capture different symbols from each pair of symbols.

The present technology relates to a reception apparatus and a data processing method that enable clock synchronization in a more suitable manner. The reception apparatus receives a digital broadcast signal of an IP transmission method that includes time information and a stream of content. The time information includes a seconds field and a nanoseconds field. The reception apparatus then generates a processing clock synchronized with the time information on the basis of the time information included in the digital broadcast signal, and processes the stream included in the digital broadcast signal on the basis of the processing clock. The present technology can be applied to, for example, television receivers conforming to the IP transmission method.

A packet network linear protection method, a network, and a node in a dual or multi-home configuration include designating each of a plurality of home nodes in the dual or multi-home configuration as a working home or a protect home; designating each link between each of the plurality of home nodes and an end node in the dual or multi-home configuration as active or standby; operating a protection switch state machine based on an associated linear protection protocol at each of the plurality of home nodes and the end node; communicating protection messages to each of the plurality of home nodes from the end node; and communicating protection states in an associated protection switch state machine by each of the plurality of home nodes to other home nodes and to the end node.

A clock synchronization method, a mobile network system, a network controller and a network switch are provided. The method computes a round-trip delay ratio between the network controller and the network switch according to a first delay, of which the network controller transmits a packet to the network switch, and a second delay, of which the network switch transmits another packet to the network controller. The method also locks a first clock based on a time-transfer protocol with the round-trip delay ratio, wherein the first clock is synchronized with a master clock of the network controller. The method further sets the first clock being locked as a runtime clock of the network switch.

A method includes receiving, by a recording device, an indication of an initializing time and receiving, by the recording device, an indication of a timing pace. The method also includes maintaining, by the recording device, an updated current time based on the initializing time and the timing pace and sensing, via a sensor of the recording device, a condition. The method further includes storing, in memory of the recording device, an indication of the condition and an associated indication of the updated current time. The indication of the updated current time corresponds to when the condition was sensed by the sensor.