Patent classifications
H04L7/0008
Cyber security anonymizer
A cyber security system for providing security to a railway, the system comprising: a data monitoring and processing hub; a network comprising a plurality of data collection agents synchronized to a same network clock and configured to monitor railway infrastructure devices and onboard devices of rolling stock having a train communication network (TCN), and forward monitored data to the hub for processing by the hub to detect anomalies in railway operation that are indicative of a cyber-attack; at least one anonymizer configured to scrub information items from data that the hub receives from a data collection agent of the plurality of data collection agents which may be used to identify the cyber security system or the railway for which the system provides security.
Signal generator
Disclosed is a method of producing an output signal from a signal generator, comprising: determining a driving input to the signal generator, the driving input for driving the signal generator to provide a predetermined output signal, wherein the output signal includes at least one frame, the at least one frame comprising an active period and a dummy period and wherein the active period and dummy period are determined by the driving input. Also disclosed is a method of producing an output signal from a signal generator, comprising: receiving a synchronisation signal; obtaining an input signal for controlling the signal generator to generate an output signal comprising at least one frame wherein the at least one frame comprises at least one active period and at least one dummy period; producing the output signal comprising a series of frames; and, synchronising the output signal with the synchronisation signal by varying a duration of the at least one of the dummy period or active period.
VLAN-aware clock synchronization
Synchronization of clocks among computing devices in a network includes determining master/slave relations among the computing devices. Some computing devices (e.g., switches) include trunk ports configured to carry traffic for several logical networks; e.g., virtual local area networks, VLANs. A trunk port can be associated with a master/slave setting for each logical network that it is configured for. Synchronization of clocks among the computing devices further includes running a synchronization sequence between a trunk port and each computing device on each of the logical networks configured on the trunk port.
Data protocol over clock line
A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.
VLAN-Aware Clock Synchronization
Synchronization of clocks among computing devices in a network includes determining master/slave relations among the computing devices. Some computing devices (e.g., switches) include trunk ports configured to carry traffic for several logical networks; e.g., virtual local area networks, VLANs. A trunk port can be associated with a master/slave setting for each logical network that it is configured for. Synchronization of clocks among the computing devices further includes running a synchronization sequence between a trunk port and each computing device on each of the logical networks configured on the trunk port.
Time synchronization method and apparatus, and storage medium
A time synchronization method, applied to a power-line communication (PLC) network that includes a head end node and at least one tail end node coupled to the head end node. The method includes the head end node generates data about voltage zero-crossing points based on reference time, where the data about the voltage zero-crossing points includes zero-crossing time points of the voltage zero-crossing points. When a first timing point arrives, the head end node sends first information to the tail end node, where the first information includes a timestamp of a first zero-crossing point, the first zero-crossing point is a voltage zero-crossing point closest to the first timing point, and the timestamp of the first zero-crossing point is used by the tail end node to determine a zero-crossing time point of a second zero-crossing point.
LOW-LATENCY, HIGH-AVAILABILITY AND HIGH-SPEED SERDES INTERFACE HAVING MULTIPLE SYNCHRONIZATION MODES
A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.
MAINTAINING A VIRTUAL TIME OF DAY
Time of day (ToD) registers provide respective virtual ToDs corresponding to the occurrence of edges of input clock signals being supplied to an integrated circuit. The integrated circuit generates a heartbeat clock signal having a frequency higher than a SYNC signal and time stamps the heartbeat clock signal to generate heartbeat time stamps. The heartbeat time stamps are used along with the time stamps of the input clock signals to determine the time of day corresponding to occurrences of edges of the input clock signals.
Dynamic Encrypted Communications Systems Using Encryption Algorithm Hopping
An apparatus for providing secure communications may include a processor; memory in electronic communication with the processor; an output in electronic communication with the processor; and instructions stored in the memory and executable by the processor to cause the apparatus to store a plurality of encryption protocols; store at least one encryption hopping protocol; select at least one encryption hopping protocol; encrypt the data according to the selected encryption hopping protocol; and transmit data from the output utilizing the selected encryption hopping protocol.
Parameter Configuration Method, Device, and System
A method, a device, and a system, the method including determining, by a management device, a first transmission path that is in a network system and that is used to transmit a clock packet of a target clock source, sending, by the management device, configuration information for the first transmission path to a plurality of network devices on the first transmission path, receiving, by the management device, information that is sent by an endpoint network device on the first transmission path and that is used to determine a time difference, and sending, by the management device, a corresponding clock compensation value to at least one network device on the first transmission path based on the information that is used to determine the time difference.