A clock port attribute recovery method includes a network device setting a value of a port attribute of a clock port of the network device to a first value based on the clock port not receiving any one of three types of clock messages: N synchronization messages, follow-up messages, and delay response messages within a timeout interval, where the first value indicates that a message is lost on the clock port. Based on a case that a recovery condition is met, the network device sets the value of the port attribute of the clock port to a second value, where the second value indicates that a status of the clock port is that the message is not lost.

The present disclosure relates to clock switching methods, devices, and storage medium. In one example method, a slave clock device may monitor a working status of a master clock device, and sends first indication information when discovering that the master clock device is in a faulty state, so that a communications device synchronizes with a system clock of the communications device based on time information of the slave clock device.

Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

A receiver includes a circuit designed to process, based on a plurality of timed waveform reference locations, a waveform signal, the waveform signal comprising a message. The circuit may include a clock source, an input configured to receive the waveform signal, a time location reference circuit coupled to the clock source, the time location reference circuit designed to output the plurality of timed waveform reference locations, each timed waveform reference location being set by the clock, and a signal processing circuit coupled to the time location reference circuit, the signal processing circuit designed to generate an output voltage in a response to the waveform signal being inputted into the signal processing circuit through the input and processed at each timed waveform reference location from the series of timed waveform reference locations. A transmitter that generates the waveform signal can be also provided where the clocks are matched.

A communication system comprising a master apparatus and a slave apparatus, wherein: the slave apparatus is configured, in an upstream period, to transmit a slave data signal to the master apparatus based on a slave clock signal; and the master apparatus is configured to: during reception of the slave data signal from the slave apparatus in the upstream period, extract timing information from the slave data signal and adjust a phase and/or frequency of a master clock signal or a definition thereof relative to a reference phase and/or frequency based on the extracted timing information to enable decoding of the received slave data signal based on the master clock signal or that definition; in a downstream period, transmit a master data signal to the slave apparatus based on the master clock signal according to the adjustment carried out during reception of the slave data signal in the upstream period; and adjust the phase and/or frequency of the master clock signal during transmission of the master data signal in the downstream period to reduce a change in the phase and/or frequency of the master clock signal effected according to the adjustment carried out during reception of the slave data signal in the upstream period.

An asynchronous medium access control layer scheduler increases efficiency for directional mesh networks by removing extra overhead in the time slots. The efficiency is increased by dividing time slots into sub-slots to allow for a receiving node to be offset by at least one sub-slot from the transmitting node. This enables the scheduler to more efficiently schedule operations for the nodes so that nodes can be performing other functions rather than waiting to receive a transmission or waiting after transmitting a transmission. The sub-slots may be sized to approximate the transmission propagation time or time of flight delay.

A method for a multichannel geophysical data acquisition system is provided in the field of electrical resistivity tomography. Individual and autonomous node operating systems are provided. Separate communication channels for upstream and downstream data transfer, high voltage transfer and synchronization signals are provided. A novel use of high voltage isolation barriers is also provided. A direct memory access data transfer process is provided.

A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.

A slave unit that is a communication apparatus according to the present invention includes: a frame relaying unit that receives, among communication frames received by a reception port, a communication frame to be relayed to the other apparatus and outputs the received communication frame to a transmission port; a frame transmitting unit that generates a communication frame and outputs the communication frame to the transmission port; and a transmission-frame arbitrating unit that regulates output of the communication frame to the transmission port performed by the frame transmitting unit in a guard time that is a period including a time period in which arrival of the communication frame transmitted in a network in a fixed cycle is expected.

A system includes a first coupled to a printed circuit board (PCB) and a second device coupled to the PCB. The system further includes a link coupled with the first device, the second device, and the PCB. The link includes a clock lane associated with associated with transmitting a clock signal and one or more data lanes corresponding to the clock lane, where the link is configured to transmit ground referenced signaling (GRS)