Various embodiments provide a data sampling circuit comprising a first sampling module configured to respond to a signal from the data signal terminal and a signal from the reference signal terminal and to act on the first node and the second node; a second sampling module configured to respond to the signal from the first node and the signal from the second node and to act on the third node and the fourth node; a latch module configured to input a high level to the first output terminal and input a low level to the second output terminal; and an offset compensation module connected in parallel to the second sampling module and configured to compensate an offset voltage of the second sampling module.

An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.

A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.

There is disclosed a method and system for controlling network timing precision of a seismic collector, and a terminal device. The method includes: using an interrupt mode to transmit a data packet; calculating an optimal network delay; and correcting a transmission error in a network timing process according to the optimal network delay, after which the physical layer of a server receives the data packet and sends the data from the physical layer of the server to the application layer of the server using the interrupt mode thereby timing the data packet.

Novel cable designs and methods for mass-manufacturing long, 100 Gbps cables suitable for large communication centers. One illustrative cable embodiment includes: at least eight pairs of electrical conductors connected between a first connector and a second connector, each of said electrical conductors being 30 AWG or smaller in cross-section and about 10 meters or longer in length, each of the first and second connectors being adapted to fit into an Ethernet port of a corresponding host device, each of the first and second connectors including a respective transceiver that performs clock and data recovery on the electrical input signal to extract and re-modulate the outbound data stream for transit via at least four of the pairs of electrical conductors as differential NRZ (non-return to zero) electrical transit signals each having a signaling rate of at least 25 GBd to convey a total of at least 100 GBd in each direction.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

The present invention is directed to communication method and techniques. In a specific embodiment, the present invention provides a receiver that interleaves data signal n-ways for n slices. Each of the n slices includes feedforward equalizer and decision feedback equalizers that are coupled to other slices. Each of the n slices also includes an analog-to-digital converter section that includes data and error slicers. There are other embodiments as well.

A method comprising: accessing a response mapping defining a set of safety-critical functions associated with a safety-critical latency threshold and a set of safety responses, each safety response corresponding to a safety-critical function; executing a time-synchronization protocol with a transmitting system to calculate a clock reference; accessing a safety message schedule indicating an expected arrival time for each safety message in a series of safety messages based on the clock reference; for each safety message in the series of safety messages, calculating a latency of the safety message based on an arrival time of the safety message and the expected arrival time; and in response to a latency of a current safety message in the series of safety messages exceeding the safety-critical latency threshold, initiating the safety response corresponding to the safety-critical function for each safety-critical function in the set of safety-critical functions.

A time synchronization method, applied to a power-line communication (PLC) network that includes a head end node and at least one tail end node coupled to the head end node. The method includes the head end node generates data about voltage zero-crossing points based on reference time, where the data about the voltage zero-crossing points includes zero-crossing time points of the voltage zero-crossing points. When a first timing point arrives, the head end node sends first information to the tail end node, where the first information includes a timestamp of a first zero-crossing point, the first zero-crossing point is a voltage zero-crossing point closest to the first timing point, and the timestamp of the first zero-crossing point is used by the tail end node to determine a zero-crossing time point of a second zero-crossing point.

A clock recovery device (10), including: a signal conversion circuit (20) that sequentially converts two consecutive symbols of a 2n+1 value (n is a natural number) pulse amplitude modulation signal to one symbol of an NRZ (Non Return to Zero) signal; and a clock recovery circuit (30) that generates a recovery clock signal from the NRZ signal converted by the signal conversion circuit. The signal conversion circuit converts the two consecutive symbols: to 0, when a second symbol is n−1 or less; to 1, when the second symbol is n+1 or more; to 0, when a first symbol is n−1 or less and the second symbol is n; to 1, when a first symbol is n+1 or more and the second symbol is n; to a conversion result of previous two symbols, when both of the two consecutive symbols are n.