A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

A frequency deviation change rate computation unit (204) computes a frequency deviation change rate being a change rate per unit time of a frequency deviation between a clock frequency of a synchronization reference device serving as a reference of time synchronization and a clock frequency of a time synchronization device which performs time synchronization with the synchronization reference device. A time correction amount computation unit (205) computes a first correction amount corresponding to a static frequency deviation between the clock frequency of the synchronization reference device and the clock frequency of the time synchronization device, performs time integration of the frequency deviation change rate to compute a second correction amount corresponding to temporal transition of the frequency deviation between the clock frequency of the synchronization reference device and the clock frequency of the time synchronization device, and computes a time correction amount for correcting a time of the time synchronization device with using the first correction amount and the second correction amount. A time correction unit (206) corrects the time of the time synchronization device with using the time correction amount.

A data transfer circuit (40) according to the invention includes a memory (41) configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit (44) configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit (42) configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit (43) configured to output, as an adjustment multiple ΔN, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit (44) generates the second clock by multiplying the reference clock by a rational number (N+ΔN) using the adjustment multiple ΔN output from the adjustment circuit (43). A data transfer circuit capable of speeding up clock synchronization can be provided.

A system for synchronizing a local audio processing clock rate of a digital signal processor (DSP) to an audio clock rate of a network to which the DSP is connected. The system includes an adjustable clock synthesizer that is configured to establish the local audio processing clock rate of the DSP. The DSP is configured to generate events that are associated with the local audio processing clock rate of the DSP. The DSP is further configured to monitor the generated events over time and based on the monitored events cause the adjustable clock synthesizer to adjust the local audio processing clock rate of the DSP to better match the network audio clock rate.

In an example, a synchronization signal can be transmitted to a plurality of synchronizers. The plurality of synchronizers can include a plurality of upstream synchronizers and a downstream synchronizer. Each synchronizer of the plurality of upstream synchronizers can be caused to count from a respective count value until a predetermined end count sequence value in response to receiving the synchronization signal. The respective count value stored at each synchronizer can be representative of a difference in time between a respective upstream synchronizer of the plurality of upstream synchronizers receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal. A respective processing element of a plurality of processing elements can be caused to start a respective function or operation in response to a respective upstream synchronizer reaching the predetermined end count sequence value.

Apparatus, methods, and computer-readable media are disclosed herein for facilitating spatial misalignment tracking for OAM beams in millimeter wave and higher frequency bands. An example method for wireless communication at a first communication device includes receiving, from a second communication device, a first misalignment tracking RS and a second misalignment tracking RS for an OAM transmission. The example method also includes determining a misalignment based on the first misalignment tracking RS, the second misalignment tracking RS, and using a subset of antenna elements of an antenna array of the first communication device. Additionally, the example method includes adjusting reception of a subsequent OAM transmission from the second communication device at the antenna array of the first communication device.

Systems and methods for time division duplex (TDD) synchronizing in distributed communication systems (DCSs) synchronize remote units operating with 5G signals by initially connecting these remote units to a 4G TDD source, and once the remote units are synchronized, switching back to a 5G TDD source. By using the downlink synchronization process of 4G instead of the normal synchronization process of 5G, the synchronization of the remote units using 5G is expedited. Further, the 5G receiver is not compressed or otherwise negatively impacted.

An embodiment method of operating a CAN bus comprises coupling a first device and second devices to the CAN bus via respective CAN transceiver circuits, and configuring the respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of messages via the CAN bus by the respective first device or second devices.

A system for synchronizing a local audio processing clock rate of a digital signal processor (DSP) to an audio clock rate of a network to which the DSP is connected. The system includes an adjustable clock synthesizer that is configured to establish the local audio processing clock rate of the DSP. The DSP is configured to generate events that are associated with the local audio processing clock rate of the DSP. The DSP is further configured to monitor the generated events over time and based on the monitored events cause the adjustable clock synthesizer to adjust the local audio processing clock rate of the DSP to better match the network audio clock rate.

Methods and devices for IQ time skew and conjugation compensation and calibration of a coherent transmitter or transceiver are described. A pilot tone is combined with a digital data signal such that relative powers of the pilot tone in each of two frequency bands of the transmitted data signal may be detected by a pilot tone detector and used to calculate the time skew between I and Q modulation channels of the transmitter. A transmitter DSP applies IQ time skew bias to the data signal to compensate for any calculated IQ time skew. The pilot tone detector also provides the transmitter DSP with the information necessary to detect phase conjugation of the optical signal, which can be corrected by inverting the polarity of the data signal or changing the phase bias point of the optical modulator.