The present disclosure provides a clock and data recovery processor for recovering timing information from a measured signal with a data input interface configured to receive samples representing the measured signal, a level comparator coupled to the data input interface and configured to determine the signal level for each of the received samples in a group comprising a predetermined number of samples, a transition comparator coupled to the level comparator and configured to compare the number of signal transitions for the samples in the group with a predetermined transition number, and a bit value determiner coupled to the transition comparator and configured to determine bit values for data symbols in the measured signal based on the detected transitions, if the transition comparator determined the number of signal transitions being equal to or larger than the predetermined transition number. Further, the present disclosure provides a measurement device and a respective method.

A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

A controller includes circuitry configured to: receive global time data indicating a global time associated with an external global clock; synchronize an internal controller clock of the controller with the global clock based on the global time; set a controller time based on the synchronized controller clock; and transmit controller time data indicating the controller time to at least one local device through periodic communication.

A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

The application provides a data extraction method for transmission signal, the data extraction method for transmission signal includes: upon receiving a transmission signal, parsing a first clock signal corresponding to the transmission signal to obtain a signal frequency; generating a second clock signal of same frequency according to the signal frequency; and extracting a data of the transmission signal according to the second clock signal. The present application aims to solve the problem of inaccurate data extraction of the transmission signal and improve the accuracy of data extraction of the transmission signal. The present application also provides a data extraction device for transmission signal and a computer readable storage medium.

A communication system (1000) includes communication devices (10, 20) to share common time after correction of synchronization error including a communication delay with each other via a network (400). The communication device (10) includes a set time acquirer to acquire set time set by a user, a setter to set the set time as first system time, which is system time of the communication device (10), and a time difference data transmitter to transmit time difference data, which indicates a time difference between the common time and the set time, to the communication device (20). The communication device (20) includes a time difference data receiver to receive the time difference data, and a setter to set the sum of the common time and the time difference indicated by the time difference data as second system time, which is system time of the communication device (20).

The present disclosure relates to a clock distribution method and apparatus in a network. A method performed at a clock distribution apparatus comprises: receiving a first clock signal; receiving a second clock signal; calculating an offset difference between the first clock signal and the second clock signal; compensating the second clock signal, based on the offset difference; and outputting a clock signal, based on the compensated second clock signal. The offset difference between the first clock signal and the second clock signal is calculated and used to compensate the second clock signal. The switching of the clock signal will be smoother for the downstream.

A communication system (1000) includes communication devices (10, 20) to share common time after correction of synchronization error including a communication delay with each other via a network (400). The communication device (10) includes a set time acquirer to acquire set time set by a user, a setter to set the set time as first system time, which is system time of the communication device (10), and a time difference data transmitter to transmit time difference data, which indicates a time difference between the common time and the set time, to the communication device (20). The communication device (20) includes a time difference data receiver to receive the time difference data, and a setter to set the sum of the common time and the time difference indicated by the time difference data as second system time, which is system time of the communication device (20).