Patent classifications
H04L7/0054
Receiver with clock recovery circuit and adaptive sample and equalizer timing
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
Method, and a synchronous digital circuit, for preventing propagation of set-up timing data errors
There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.
Method for receiving control in-formation for reference signal related to phase noise estimation and user equipment therefor
A method for receiving control information for a reference signal related to phase noise estimation by a user equipment (UE), the method including receiving control information indicating whether the reference signal related to the phase noise estimation is transmitted; and when the control information indicates that the reference signal is transmitted, receiving the reference signal based on the control information. When a size of a traffic resource block (RB) for the UE is greater than a predetermined value, the control information indicates the reference signal is transmitted.
Information processing device and management device
An information processing device which transmits and receives a message to which a communication ID indicating a class has been assigned, includes: a storage unit which stores, for each of the communication IDs, a communication counter for verifying a recency of a communication; a recency information management unit which updates the communication counter based on a predetermined condition; an abnormality monitoring unit which identifies an influence range of an abnormality that occurred; and a message generation unit which generates a synchronization request message including the communication ID indicating that it is a message requesting a synchronization of the communication counter, and a synchronization target identifier indicating the influence range identified by the abnormality monitoring unit.
SYSTEMS AND METHODS OF CONTROLLING SYNCHRONICITY OF COMMUNICATION WITHIN A NETWORK OF DEVICES
A communication system controller having an input for receiving output signals of a sending device. The communication system controller further has a clock signal. The communication system controller further has an output for transmitting input signals to a target device. The communication system controller further has a signal processing element capable of determining if the received output signals of the sending device are synchronous with the clock signal. The signal processing element is further capable of determining if the received output signals of the sending device are asynchronous with the clock signal. The communication system controller is capable of transmitting the received output signals of the sending device as input signals to the target device if the received output signals of the sending device are determined to be synchronous with the clock signal.
METHOD AND APPARATUS FOR PROCESSING SIGNAL IN WIRELESS COMMUNICATION SYSTEM
The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate than 4G communication systems such as LTE systems. A method performed by a user equipment (UE) in a wireless communication system may comprise receiving a signal, converting the signal into a digital signal, receiving, from a base station, transmission spectrum information for the UE and information for a time window, estimating a timing skew and a reception signal-to-noise ratio (SNR) of the digital signal based on the information for the time window and the transmission spectrum information, and compensating for a distortion of the digital signal based on the estimated timing skew and the reception SNR.
System and method for clock resynchronization
A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.
SYNCHRONIZATION CONTROL APPARATUS AND SYNCHRONIZATION CONTROL METHOD
According to one embodiment, there is provided a synchronization control apparatus which synchronizes an STC counter value, based on TAI (Temps Atomique International: international atomic time) time, in each of systems which constitute a transmission system in a broadcasting system or a distribution system, the apparatus includes a processor or a dedicated arithmetic circuit configured to determine a time length in which the STC counter value laps, to calculate a remainder of the time length relative to the TAI time, and to convert the remainder to the STC counter value, thereby determining the STC counter value.
TRANSMITTING CIRCUIT, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM CONFIGURED TO USE THE TRANSMITTING CIRCUIT
A transmitting circuit may include a clock generation circuit and a serializer. The clock generation circuit may generate a plurality of output clock signals by performing an emphasis operation for a plurality of clock signals based on a plurality of data. The serializer may output the plurality of data as output data in synchronization with the plurality of output clock signals.
Communication device and orthogonal error measurement method for communication device
According to an embodiment, a communication device includes a phase-shifting circuit that shifts a phase of a local signal and supplies it to an orthogonal demodulator. The phase-shifting circuit includes first and second signal input ends that are supplied with an output signal of a local oscillator between both ends thereof, a frequency divider that has first and second input ends, and a switching part that is provided between the first and second signal input ends and the first and second input ends of the frequency divider and switches connection between the first and second signal input ends and the first and second input ends of the frequency divider.