Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

Systems and methods for phase detection are disclosed. Phase alignment between first and second clock signals is detected using a comparison of outputs from a collapsible pipeline and a non-collapsible pipeline.

Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

A transmission apparatus including: a first transferer that transfers first data including first identification information; a second transferer that transfers second data including second identification information; a detector that detects the first identification information from the first data transferred from the first transferer; and a storage that stores the second data transferred from the second transferer; wherein the detector detects the second identification information from the second data stored into the storage after detecting the first identification information from the first data.

Methods and systems are provided for guard band detection and frequency offset detection. For each of a plurality of downconverted signals, frequency related information associated with one or more corresponding circuits used in obtaining the plurality of downconverted signals may be determined; and based on the determined frequency related information, one or both of a band stacking operation and a channel stacking operation may be performed. During the band stacking operation, frequency bands are not stacked on each other or stacked frequency bands do not overlap. During the channel stacking operation, channels are not stacked on each other or stacked channels do not overlap. The frequency related information may be determined based on predefined frequency related parameters associated with the corresponding circuits. Frequency corrections may be performed, on output signals corresponding to the band stacking operation and/or the channel stacking operation, based on the frequency related information.

In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to determine a lowest latency LAG port for each LAG in any path of a plurality of paths connecting a first device with a second device, and discover a configuration of a network fabric connecting the first device to the second device after determining the lowest latency LAG port for each LAG therein. The network fabric includes a plurality of devices interconnected with LAGs. Moreover, the embodied program instructions are executable by the processor to perform clock synchronization for each path of the plurality of paths and determine a latency for each path of the plurality of paths based on the clock synchronization and the lowest latency LAG port for each LAG included in the plurality of paths.

A data processing system includes a master device and a slave device. The master device includes a first single pad, a first control circuit, a first frame generator configured, and a first processing circuit. The slave device includes a second single pad, a second control circuit, a second frame generator, and a second processing circuit. A clock source is configured to provide a clock signal to the master device and the slave device. The master device communicates with the slave device through a single wire, the single wire being connected between the first single pad and the second single pad, wherein the single wire is bidirectional. A first frame is transmitted from the master device to the slave device, and a second frame is transmitted from the slave device to the master device.

Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.

Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link. The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.

Implementations described herein relate to methods, systems, and computer-readable media for self-healing network timekeeping. A method can include monitoring a plurality of computing devices described in network topology data of a computer network, receiving asynchronous network configuration data from a computing device, the asynchronous network configuration data including at least one timekeeping value, determining that at least one timekeeping value exceeds a network timekeeping threshold, responsive to the determining, comparing a root of time in the asynchronous network configuration data with the network topology data to identify at least one network timekeeping configuration error, generating a list of actions to repair the network timekeeping configuration error, and directing the computing device to perform the list of actions.