Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.

Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.

A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

In a phase error corrector, a signal extractor extracts received reference signals from received signals, and an error vector calculator calculates the error vectors of phase errors by comparing the extracted received reference signals with a known reference signal that is to be transmitted. A representative vector calculator divides, according to frequency, the error vectors into two or more groups and calculates representative vectors for the respective groups. A correction value calculator calculates, on the basis of the representative vectors, phase correction values for the respective frequencies. A phase corrector uses the calculated phase correction values to correct the phase errors for the respective frequencies.

A robust frequency drift tracking receiver. The received signal is translated to an intermediate frequency in the RF stage by a quadrature demodulator, and is then brought into the base band by a digital mixer made by a CORDIC. A base band processing, stage allows for a synchronisation of the receiver relative to the data frame, to estimate data and to output a counter-reaction signal to the CORDIC, obtained by integration of successive frequency corrections with a predetermined step.

Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Systems and methods are described that enable user terminals to eliminate or reduce the number of dummy bursts (or bursts with no data) they send. The systems and methods use two burst detectors, a first burst detector that analyzes the physical structure of the signal, and a second burst detector that analyzes the informational structure of the signal. Output from the first burst detector can be used to control operation of a signal decoder that decodes received signals. The second burst detector analyzes output from the signal decoder to determine the second burst indicator. In other words, the first burst detector can be implemented prior to decoding the received signal to provide a first estimate related to the presence or absence of a burst. This can then be used to limit the amount of processing performed by the signal decoder.

Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

A system may include a first device, a second device, a third device, and a serial link between the second device and the third device. The first device may be configured to deliver to the second device an information stream having a transmission fault tolerance associated with a transmission by the second device to the third device over the serial link. A related method may include, during the transmission over the serial link, phases for synchronization between the second and third devices, and during each synchronization phase, the first device may continue to deliver the information stream to the second device.