A method for compensating for a sampling clock-offset includes calculating a positive threshold and a negative threshold of pulse-shaped data symbols to be received, calculating a positive sum ratio and a negative sum ratio from received samples, and compensating for a sampling clock-offset in response to the positive sum ratio being less than or equal to the positive threshold and the negative sum ratio being less than or equal to the negative threshold.

In order to reduce ambiguity in NB-SSS and complexity of receiver processing, a transmitter apparatus generates an SSS, wherein the SSS signal comprises a sequence of OFDM symbols, wherein each symbol of the sequence of SSS symbols is mapped to a codeword symbol of an FEC code. Source symbols of the sequence of SSS symbols carry a PCID and frame timing information, and parity symbols of the sequence of SSS symbols introduce redundancy and coding gain. A receiver receives the NB-SSS over multiple OFDM symbols, each symbol of the SSS comprising a short ZC sequence with a combination of root index and cyclic shift. The apparatus derives path metrics using cross-correlation for each of the plurality of symbols, determines a candidate SSS source message based on the derived path metrics and coding constraints of FEC codewords, and identifies a PCID and timing information based on the candidate SSS source message.

In an embodiment, a receiver detects a timing error between a transmitter clock at a transmitter and a receiver clock at a receiver associated with an exchange of CPM signals. The receiver phase aligns input samples of a candidate received signal over a time window based on a rotating signal corresponding to a phase progression of the candidate received signal. The receiver generates first and second partial sums of the phase-aligned input samples that are accumulations of phase-aligned input samples corresponding to modulation symbols that contribute positive and negative phases, respectively, to the phase progression. The receiver determines a phase difference between the first and second partial sums, and generates a timing-error metric that is indicative of a timing error between the transmitter clock and the receiver clock based at least in part upon the determined phase difference.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Embodiments herein describe sub-picosecond accurate two-way clock synchronization by optically combining received optical pulses with optical pulses generated locally in a photonic chip before the optical signals are then detected by a photodetector to obtain an interference measurement. That is, the optical pulses can be combined to result in different interference measurements. Optically combining the pulses in the photonic chip avoids much of the jitter introduced by the electronics. Further, the sites can obtain multiple interference measurements which can be evaluated to accurately determine when the optical pulses arrive at the site with femtosecond accuracy.

An optical reception device according to an exemplary aspect of the invention includes an optical front-end means for demodulating an inputted optical signal, converting the demodulated signal into an electrical signal and outputting the electrical signal, a pre-emphasis means for adding a high frequency component to the electrical signal, a digital signal processing means for receiving input of the electrical signal with the high frequency component added thereto via a transmission wire, and for performing a digital coherent reception process on the inputted electrical signal, an error detection means for detecting a signal error in the digital coherent reception process and a feedback control means for varying the level of a high frequency component added at the pre-emphasis means and, in accordance with signal errors detected at that time, controlling the pre-emphasis means.

A method and system for the post-adjustment (i.e., offline) of event timestamps to implement virtual time synchronization amongst detection node clocks. In existing methodologies with the goal of clock synchronization, clocks (and timestamps generated therefrom) are disciplined or adjusted at the recordation time of the events on a detection node (e.g., a switch/router, an Internet-of-Things (IoT) device, a wireless sensor, etc.). However, there is no particular reason for these clocks or timestamps to be accurate during the recordation time, but rather, should be accurate at their use or interpretation time. Further, through these recordation time adjustments, clock drifts and timing errors may be gradually introduced, leading to runaway inaccuracies. The disclosed method and system intentionally avoids the disciplining of clocks at event recordation times on the detection node and, instead, adjusts timestamps during interpretation times, to overcome the aforementioned issues.

A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defined number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.

Provided is a method for calculating a timestamp associated with a data packet before transcoding of the data packet. The method may include sampling a time of day (TOD) signal to provide a sampled TOD. A previously sampled TOD estimate may be retrieved. An internal TOD estimate may be determined based on the sampled TOD and the previously sampled TOD estimate. A timestamp may be determined based on the internal TOD estimate. A system and computer program product are also disclosed.

A sequence of symbols is received on a first channel. A noise contribution of a given synchronization symbol is estimated; a reference noise contribution of at least one further symbol is estimated. Based on the noise contribution and further based on the reference noise contribution the given synchronization symbol is selectively considered when determining a coupling coefficient of crosstalk between the first channel and a second channel.