A method for receiving an ADS-B message is disclosed including a synchronisation phase for detecting the start of the message and a decoding phase for recovering a bit stream corresponding to a block of data in the message. The synchronisation phase is based on determining a sequence of log-likelihood ratios having the greatest likelihood of corresponding to a sequence of symbols expected from a preamble of the message. Each log-likelihood ratio corresponds to a ratio between the respective probabilities that a symbol of the signal received corresponds to one of two possible values for a symbol. The decoding phase applies a belief propagation algorithm to a sequence of log-likelihood ratios respectively associated with the symbols in the block of data in the message, with an optimised parity matrix of the cyclic redundancy code of the message.

Embodiments herein describe sub-picosecond accurate two-way clock synchronization by optically combining received optical pulses with optical pulses generated locally in a photonic chip before the optical signals are then detected by a photodetector to obtain an interference measurement. That is, the optical pulses can be combined to result in different interference measurements. Optically combining the pulses in the photonic chip avoids much of the jitter introduced by the electronics. Further, the sites can obtain multiple interference measurements which can be evaluated to accurately determine when the optical pulses arrive at the site with femtosecond accuracy.

A signal analysis method is described. The signal analysis method includes: receiving a time-and-value discrete input signal, the input signal being associated with a signal source; determining at least one jitter component of the input signal; determining a step response based on the input signal, the step response being associated with at least the signal source; determining a counter function based on the step response, the counter function being configured to cancel error terms in a finite-time transform of the step response to frequency domain; superposing the step response and the counter function, thereby obtaining a modified step response; and transforming the modified step response to frequency domain, thereby obtaining a transfer function being associated with at least the signal source. Further, a signal analysis module for analyzing a time-and-value discrete input signal being associated with a signal source is described.

A signal processing method includes receiving a digital signal including a sequence of samples. For each sample among at least some of the samples, a neighbor-based estimate is calculated over (i) one or more samples that precede the sample in the sequence and (ii) one or more samples that succeed the sample in the sequence, and an error value, indicative of a deviation of the neighbor-based estimate from an actual value of the sample, is calculating. An impairment in the digital signal is estimated based on a plurality of error values calculated for a plurality of the samples.

A leader system for time synchronizing includes an interface and a processor. The interface is configured to receive a time standard. The processor is configured to determine whether a time jump is necessary in response to the time standard; and in response to determining that the time jump is necessary: 1) cause overwriting a sensor data buffer; 2) provide an indication to unregister one or more follower devices from a leader device; and 3) time jump a leader device time in response to the time standard.

Provided is a method for calculating a timestamp associated with a data packet before transcoding of the data packet. The method may include sampling a time of day (TOD) signal to provide a sampled TOD. A previously sampled TOD estimate may be retrieved. An internal TOD estimate may be determined based on the sampled TOD and the previously sampled TOD estimate. A timestamp may be determined based on the internal TOD estimate. A system and computer program product are also disclosed.

A signal analysis method is described. The signal analysis method includes: receiving a time-and-value discrete input signal, the input signal being associated with a signal source; determining at least one jitter component of the input signal; determining a step response based on the input signal, the step response being associated with at least the signal source; determining a counter function based on the step response, the counter function being configured to cancel error terms in a finite-time transform of the step response to frequency domain; superposing the step response and the counter function, thereby obtaining a modified step response; and transforming the modified step response to frequency domain, thereby obtaining a transfer function being associated with at least the signal source. Further, a signal analysis module for analyzing a time-and-value discrete input signal being associated with a signal source is described.

Provided are a device synchronization method and apparatus, a device, and a storage medium. The device synchronization method includes: in response to determining that a second device does not receive a first data packet, determining a target time cycle for sending data packets by the second device based on a preset cycle adjustment parameter and a preset time slice length; determining whether the second device receives a second data packet sent by the first device based on the time slice length and the target time cycle of the second device; and in response to determining that the second device receives the second data packet sent by the first device, determining a time point for sending a data packet next time by the second device according to data packet information of the first device, achieving cycle synchronization of the second device in a preset synchronization cycle time period.

A network element, for use in an automotive network in a vehicle, includes one or more ports, packet processing circuitry and a validation data collector. The one or more ports are configured for communicating over the automotive network in the vehicle. The packet processing circuitry is configured to receive packets from the automotive network via the one or more ports, the packets including time-protocol packets, to process the received packets, and to forward the processed packets to the automotive network via the one or more ports. The validation data collector is configured to derive, from at least some of the time-protocol packets that are processed by the packet-processing circuitry, validation data indicative of compliance of the network element with a vehicle-safety requirement, and to make the validation data accessible from outside the network element.

Noise test systems, methods, and circuitries are provided for determining a phase error of a first modulator using a second modulator. In one example, an integrated circuit device includes a first modulator configured to modulate a first signal to generate a first modulated signal and a second modulator configured to modulate a second signal to generate a second modulated signal. The first signal and the second signal are based on the same reference signal. The integrated circuit device also includes analysis circuitry configured to determine a phase error of the first modulator based on the first modulated signal and the second modulated signal.