A transport framework for heterogeneous data streams includes session management module and a connection management module. The session management module is configured to receive a request to establish a first stream that is used for transmitting or receiving data, where the request includes an express indication as to whether the first stream is reliable or unreliable; construct a first data frame based on application data; handoff the first data frame to the connection management module; and maintain a record for the first data frame that includes whether the first data frame is successfully transmitted to the receiver. The connection management module is configured to receive the first data frame of the first stream from the session management module; receive a second frame from the session management module; encapsulate the first data frame and the second frame in a packet; and transmit the packet to the receiver using an unreliable protocol.

Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.

A system and method for configuring a serial receiver. In some embodiments, the method, includes: setting a threshold of a data slicer to a first threshold value; receiving, by the data slicer, a first data value; and setting the threshold of the data slicer to a second threshold value, the second threshold value being equal to the first threshold value plus a first adjustment, the first adjustment having the same sign as the first data value minus the first threshold value.

A 100BASE-TX transceiver includes a receive (RX) circuit, a transmit (TX) circuit, a clock generator circuit, a clock and data recovery (CDR) circuit, and a clock multiplexer circuit. The RX circuit receives an input data to generate an RX data. The TX circuit transmits a TX data according to a TX clock, to generate an output data. The clock generator circuit generates an output clock. The CDR circuit generates an RX recovered clock according to the RX data. The clock multiplexer circuit receives the output clock and the RX recovered clock, and outputs the TX clock that is selected from the output clock and the RX recovered clock.

Included are a demodulation unit that demodulates a received OFDM modulation signal to acquire a demodulated constellation signal, an ideal constellation signal generation unit that generates an ideal constellation signal from the demodulated constellation signal, a data extraction unit that extracts signal data corresponding to subcarriers included in a part of an intermediate frequency section among all frequency sections, from the demodulated constellation signal and the ideal constellation signal, a phase error calculation unit that calculates the phase error of the demodulated constellation signal for the ideal constellation signal, with respect to the extracted signal data, a phase error characteristic estimation unit that estimates the frequency characteristic of the phase error, and a phase error correction unit that corrects the phase error of the demodulated constellation signal, based on the frequency characteristic of the phase error.

A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

A method applicable to a receiver circuit, including: performing a cross-correlation operation upon at least one time-domain signal on at least one receiver path of the receiver circuit according to a local sequence signal, to estimate at least one time offset amount of the at least one time-domain signal as at least one time offset compensation amount; and, performing time offset compensation upon the at least one time-domain signal on the at least one receiver path according to the at least one time offset compensation amount.

Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.