The present disclosure provides a clock and data recovery processor for recovering timing information from a measured signal with a data input interface configured to receive samples representing the measured signal, a level comparator coupled to the data input interface and configured to determine the signal level for each of the received samples in a group comprising a predetermined number of samples, a transition comparator coupled to the level comparator and configured to compare the number of signal transitions for the samples in the group with a predetermined transition number, and a bit value determiner coupled to the transition comparator and configured to determine bit values for data symbols in the measured signal based on the detected transitions, if the transition comparator determined the number of signal transitions being equal to or larger than the predetermined transition number. Further, the present disclosure provides a measurement device and a respective method.

Provided are a data signal detection device, and mobile industry processor interface radio frequency front-end device and system. The device includes: a first acquisition circuit, a second acquisition circuit and a selection output circuit. A first input terminal of the first acquisition circuit is connected to a second input terminal of the second acquisition circuit, and a second input terminal of the first acquisition circuit is connected to a first input terminal of the second acquisition circuit. Output terminals of the first acquisition circuit and the second acquisition circuit are connected to two input terminals of the selection output circuit. The acquisition circuit is configured to verify whether an acquisition signal meets a characteristic of a data signal; and the selection output circuit selects an acquisition signal from a received acquisition signal and a received invalid signal for output.

A method for detecting a constant envelope burst-mode radio frequency (RF) signal with a known periodic synchronization sequence (PSS) represented therein, e.g. to be for reading of data from utility meters. An incoming RF signal is transformed into a digital baseband signal (DBS), and the phase domain part is processed by: 1) applying a correlation algorithm to correlate the DBS with a synchronization pattern corresponding to the PSS. 2) filtering the resulting correlation signal for removing at least a DC component of the correlation signal. 3) down-sampling the filtered correlation signal (or the correlation signal) with a sampling time controlled by a clock aligned with amplitude peaks in the filtered correlation signal (or the correlation signal). 4) performing a decision algorithm on the down-sampled signal to determine if PSS is present in the incoming RF signal. Then, 5) generating an output signal indicating if the known PSS is present in the incoming RF signal, in response to a result of the decision algorithm. The steps 1)-5) serve to detect if an amplitude in the correlation signal indicates the presence of the known PSS. Preferably, a second decision algorithm serves to detect if periodicity in the correlation signal indicates the presence of the known PSS, and finally the results of the first and second decision algorithms can be combined, e.g. by a logic AND operation, to arrive at a sensitive and reliable PSS detection result.

Various example embodiments relate to partial data transmission. A transmitter may receive at least one dataset for transmission. The dataset may be one of a plurality of datasets known to the transmitter and a receiver or to be signaled to the receiver. The transmitter may determine a first portion of the dataset. The size of the first portion may be determined based on a battery level indicator, a latency level associated with the dataset, a radio condition, or a network load. The receiver may recognize the dataset based on the first portion and/or at least one second portion transmitted by the transmitter. Apparatuses, methods, and computer programs are disclosed.

In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.

A communication method, device, and a storage medium to resolve a problem that information about a clock frequency and a clock phase of a service cannot be correctly transmitted to a receiver or correctly recovered because transparent transmission of the information about the clock frequency and the clock phase of the service cannot be implemented. Because a value of k based on a reference data unit is inserted into a second data flow, and the value of k can indicate a quantity of third data units included between a second data unit and the reference data unit in a first data flow, a receive end device can completely recover the first data flow based on the value of k.

A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

A method for synchronizing networks is disclosed. A first wired communication system having a first time base is set up in a first network. A second wired communication system having a second time base is set up in a second network. The first network and the second network are connected to a wireless communication system via a first translation unit and a second translation unit, respectively. The first translation unit and the second translation unit are synchronized to one another according to a third time base of the wireless communication system independently of the first time base and the second time base. A third synchronization message is transmitted from the first translation unit to the second translation unit. A transmission time for the third synchronization message in the third time base is determined and is used to synchronize the second time base to the first time base.

A receiver generates a stream of digital samples from an analog electrical signal that represents data conveyed to the receiver over a communication channel, where the stream of digital samples comprises current samples corresponding to a current timepoint, previous samples corresponding to a timepoint earlier than the current timepoint, and subsequent samples corresponding to a timepoint later than the current timepoint. The receiver generates previous, current, and subsequent phase offset signals based on the previous, current, and subsequent samples, respectively. The receiver uses the previous phase offset signal to adjust clock frequency and clock phase of the current samples, thereby resulting in current adjusted samples. The receiver adjusts clock phase of the current adjusted samples based on any one of the previous, current, and subsequent phase offset signals. In some examples, receiver adjusts the clock phase of the current adjusted samples based on the subsequent phase offset signal.

A receiver generates a stream of digital samples from an analog electrical signal that represents data conveyed to the receiver over a communication channel, where the stream of digital samples comprises current samples corresponding to a current timepoint, previous samples corresponding to a timepoint earlier than the current timepoint, and subsequent samples corresponding to a timepoint later than the current timepoint. The receiver generates previous, current, and subsequent phase offset signals based on the previous, current, and subsequent samples, respectively. The receiver uses the previous phase offset signal to adjust clock frequency and clock phase of the current samples, thereby resulting in current adjusted samples. The receiver adjusts clock phase of the current adjusted samples based on any one of the previous, current, and subsequent phase offset signals. In some examples, receiver adjusts the clock phase of the current adjusted samples based on the subsequent phase offset signal.