A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

A receiver is configured to receive a series of command signals and a series of data signals. The receiver includes a first clock and data recovery (CDR) circuit, a control circuit and a second CDR circuit. The first CDR circuit is configured to process the series of command signal to generate a clock signal. The control circuit, coupled to the first CDR circuit, is configured to generate a control signal according to the series of command signals and the clock signal received from the first CDR circuit. The second CDR circuit, coupled to the control circuit, is configured to process the series of data signals according to the control signal received from the control circuit.

The present invention provides a receiver including a filter, a signal detection circuit and a synchronization processing circuit. The filter is configured to filter a filter input signal to generate a filter output signal. The signal detection circuit is configured to determine whether the filter input signal or the filter output signal includes an interference signal according to the filter input signal and the filter output signal, to generate an interference signal indicator; wherein when the interference signal indicator indicates that the filter input signal or the filter output signal includes the interference signal, the signal detection circuit further determines whether the filter output signal comprises an effective signal to generate an effective signal indicator. The synchronization processing circuit is configured to process the filter output signal according to the interference signal indicator and the effective signal indicator.

A transmission device includes a receiver configured to receive a frame signal including synchronization data, main signal data, and an error correction code, a compensator configured to compensate for distortion of the frame signal based on a compensation coefficient, a detector configured to detect synchronization timing of the frame signal from the synchronization data; a corrector configured to correct an error of the frame signal after the distortion is compensated, based on the error correction code according to the synchronization timing, a generator configured to generate a replica signal from the frame signal after the error is corrected by the corrector, based on the synchronization timing, the replica signal corresponding to the frame signal before the distortion is compensated, and an update processor configured to update the compensation coefficient based on the replica signal and the frame signal before the distortion is compensated.

Devices and methods that receive timing information from at least one source clock in a network that exchanges data packets conforming to the Internet Protocol. The timing information preferably includes a time-to-live (TTL) field in a packet header used to: select a source of timing information; configure a PTP port, or both.

Various example embodiments relate to partial data transmission. A transmitter may receive at least one dataset for transmission. The dataset may be one of a plurality of datasets known to the transmitter and a receiver or to be signaled to the receiver. The transmitter may determine a first portion of the dataset. The size of the first portion may be determined based on a battery level indicator, a latency level associated with the dataset, a radio condition, or a network load. The receiver may recognize the dataset based on the first portion and/or at least one second portion transmitted by the transmitter. Apparatuses, methods, and computer programs are disclosed.

In some aspects, the disclosure is directed to methods and systems for synchronized multi-client content delivery, and a content selection system based on individual and aggregated scores for the content items, to generate bundles or sets of content items having approximately corresponding scores. Server timers and local timers on client devices may be synchronized via notifications, and timer durations dynamically adjusted when client requests and responses are sent prior to client-side timer expiration, but received after server-side timer expiration, indicating communication latency has caused desynchronization. Timers may be adjusted on a global basis or per-client device basis. Through scoring and bundling, sets of content items that may be relevant to approximately an equal share of the recipient client devices may be selected and transmitted.

A clock and data recovery device and a jitter tolerance enhancement method thereof are provided. The clock and data recovery device includes a clock and data recovery circuit and a jitter tolerance enhancement circuit. A data input terminal of the clock and data recovery circuit is suitable for receiving a data signal. The clock and data recovery circuit recovers the data signal to a clock. The jitter tolerance enhancement circuit is coupled to the data input terminal of the clock and data recovery circuit to receive the data signal. The jitter tolerance enhancement circuit detects a correlation between the data signal and the clock and correspondingly adjusts a loop gain of the clock and data recovery circuit according to the correlation.

A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

Novel cable designs and methods for mass-manufacturing long, 100 Gbps cables suitable for large communication centers. One illustrative cable embodiment includes: at least eight pairs of electrical conductors connected between a first connector and a second connector, each of said electrical conductors being 30 AWG or smaller in cross-section and about 10 meters or longer in length, each of the first and second connectors being adapted to fit into an Ethernet port of a corresponding host device, each of the first and second connectors including a respective transceiver that performs clock and data recovery on the electrical input signal to extract and re-modulate the outbound data stream for transit via at least four of the pairs of electrical conductors as differential NRZ (non-return to zero) electrical transit signals each having a signaling rate of at least 25 GBd to convey a total of at least 100 GBd in each direction.