A method and system of synchronizing a local clock with a master clock using a serial communication bus includes receiving by a serial data interface receiver a master time signal corresponding to a master clock, generating by a frequency tuning loop a time error signal corresponding to a difference between the master time signal and a local time signal, generating by the frequency tuning loop an actual frequency signal based on a base frequency and the time error signal, producing by the frequency tuning loop a command frequency error based on the actual frequency signal and the local time signal, and producing by the local clock an updated local time signal based on the command frequency error.

A method and apparatus according to the present invention addresses and/or prevents lost protocol synchronization in HARQ systems caused by ACK/NACK errors. One embodiment detects lost synchronization errors for NDI-based retransmission protocols and restores synchronization by sending an explicit RESET message. In response to the RESET message, the transmitter aborts the transmission of a current PDU and transmits a new PDU and corresponding NDI. Another embodiment prevents protocol synchronization errors by sending scheduling grants on a packet by packet basis. The receiver sends a subsequent explicit scheduling grant to the transmitter based on an error evaluation of a received PDU. The transmitter will not send the next PDU unless it receives the subsequent explicit scheduling grant.

A system for generating a self-receive signal includes: a signal generator; a first signal processor; a second signal processor; and an antenna. The system also includes a first passive coupling device: defining a first input port electromagnetically coupled to the signal generator; defining a first transmitted port; defining a first coupled port electromagnetically coupled to the first signal processor; and characterized by a first phase balance between the first transmitted port and the first coupled port. The system further includes a second passive coupling device: defining a second input port electromagnetically coupled to the antenna; defining a second transmitted port electromagnetically coupled to the first transmitted port; defining a second coupled port electromagnetically coupled to the second signal processor; and characterized by a second phase balance between the second transmitted port and the second coupled port substantially similar to the first phase balance.

the present invention provides a millimeter-wave up/down converter, with an internal signal source therein capable of manual coarse tuning and fine tuning, used for receiving and converting a low frequency/high frequency signal into a high frequency/low frequency signal to be used by a device in a user terminal, and comprises a micro-controller module, an adjusting switch, and a frequency-converter module. The micro-controller module is provided therein with a frequency control signal with a frequency within a frequency range. The adjusting switch is connected to the micro-controller module for adjusting the frequency control signal; thereby the adjusted frequency control signal is outputted from the micro-controller module. The frequency-converter module is connected to the micro-controller module to receive the adjusted frequency control signal, such that after further receiving an external low frequency and high frequency signal, the frequency-converter module generates and outputs the high frequency/low frequency signal.

Some implementations of the disclosure are directed to symbol-timing tracking systems and methods. A symbol-timing tracking system may include: an ADC to generate a digital signal by sampling an analog signal received at a receiver; an interpolator to adjust a sampling rate of the digital signal; a receive filter to apply a receive filtering function to the digital signal to generate a filtered signal; a timing error detector configured to generate a timing error signal from the filtered signal; a high-order loop filter to filter the timing error signal to generate a filtered timing error signal; and a numerically controlled oscillator to control timing data based on the filtered timing error signal and provide the timing data to the interpolator, wherein the interpolator is to correct for timing of the digital signal and adjust the sampling rate of the digital signal based on the timing data.

A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

A method of calibrating a clock phase and a voltage offset includes receiving an input data signal that is periodically toggled. A clock phase calibration operation is performed based on an up signal and a down signal, such that phases of a plurality of clock signals are adjusted. The up signal and the down signal are generated based on the input data signal, a reference voltage and the plurality of clock signals. A voltage offset calibration operation is performed based on the up signal, the down signal and a first sample data signal, such that a voltage level of the reference voltage is adjusted. The first sample data signal is generated by sampling the input data signal based on one of the plurality of clock signals. The clock phase calibration operation and the voltage offset calibration operation are performed independently of each other and not to overlap with each other.

Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.

A data receiving apparatus of the present disclosure includes a first phase adjustment circuit and a second phase adjustment circuit. The first phase adjustment circuit performs a phase adjustment between multiple data signals received via multiple data signal lines. The second phase adjustment circuit performs a phase adjustment of a clock signal received via a clock signal line with respect to the multiple data signals after the phase adjustment between the multiple data signals is performed by the first phase adjustment circuit.

A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include processing circuitry configured to control the clock and data recovery circuit. The processing circuitry and the clock and data recovery circuit may be formed on a single substrate.