A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

This application is directed to an electronic device including a phase locked loop (PLL) circuit. The PLL includes a voltage-controlled oscillator (VCO) and the PLL is configured to generate a plurality of periodic signals having a first frequency. Optionally, the periodic signals are equally separated in phase to cover an entire period cycle of the first frequency. The electronic device includes a first multiplexer coupled to the PLL, the first multiplexer being external to the PLL. The first multiplexer configured to receive a first selection signal, select a first periodic signal of the plurality of periodic signals based on the first selection signal, and provide the first selected periodic signal to a first clock-driven circuit that is distinct from the PLL. The electronic device further includes a controller circuit coupled to the first multiplexer, the controller circuit being configured to provide the first selection signal to the first multiplexer.

An electronic device includes a receiver circuit, a clock generator circuit, and a clock control circuit. The receiver circuit receives first clock information associated with a first clock of another electronic device. The clock generator circuit generates a second clock for the electronic device. The clock control circuit obtains second clock information associated with the second clock, generates a clock control signal according to the first clock information and the second clock information, and outputs the clock control signal to the clock generator circuit, where the clock generator circuit adjusts the second clock in response to the clock control signal.

There is provided a reception device including a data signal receiver circuit, a clock signal receiver circuit, and a discrimination circuit. The data signal receiver circuit receives a data signal through a data signal line, and receives a data blanking signal through the data signal line in a blanking period of the data signal. The clock signal receiver circuit receives a clock signal and a clock blanking signal through a clock signal line, the clock blanking signal outputted in synchronization with the blanking period of the data signal. The discrimination circuit discriminates communication modes on a basis of one or both of a signal value of the data blanking signal and a signal value of the clock blanking signal.

A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.

Embodiments of this application provide a clock phase recovery apparatus and method, and a chip. The clock phase recovery apparatus includes an ADC, a dispersion compensation unit, a digital interpolator, a MIMO equalization unit, and a clock offset phase obtaining unit. The ADC is connected to the dispersion compensation unit, and the dispersion compensation unit is connected to a first input end of the digital interpolator. An output end of the digital interpolator is connected to an input end of the MIMO equalization unit, and an output end of the MIMO equalization unit is connected to an input end of the clock offset phase obtaining unit. The digital interpolator is configured to adjust, based on first offset phase information output by the clock offset phase obtaining unit, a dispersion-compensated signal output by the dispersion compensation unit.

A system for generating a self-receive signal includes: a signal generator; a first signal processor; a second signal processor; and an antenna. The system also includes a first passive coupling device: defining a first input port electromagnetically coupled to the signal generator; defining a first transmitted port; defining a first coupled port electromagnetically coupled to the first signal processor; and characterized by a first phase balance between the first transmitted port and the first coupled port. The system further includes a second passive coupling device: defining a second input port electromagnetically coupled to the antenna; defining a second transmitted port electromagnetically coupled to the first transmitted port; defining a second coupled port electromagnetically coupled to the second signal processor; and characterized by a second phase balance between the second transmitted port and the second coupled port substantially similar to the first phase balance.

A system for generating a self-receive signal including: a signal generator; a signal processor including an analog-to-digital converter; and an antenna. The system also includes a passive coupling device including: an antenna port electromagnetically coupled to the antenna; a transmit port electromagnetically coupled to the signal generator; and a receive port electromagnetically coupled to the signal processor. The system additionally includes an impedance matching network: electromagnetically interposed between the antenna port and the antenna; and configured to shift an impedance of the antenna to a load impedance different from a characteristic impedance of the passive coupling device. The antenna and the passive coupling device of the system cooperate to reflect the signal, transmitted via the transmit port, toward the receive port at a receive voltage between the input noise floor and the input saturation voltage according to a reflection coefficient based on the load impedance and the characteristic impedance.

A controller area network receiver includes a measurement circuit, a filter circuit, and a frame detection circuit. The measurement circuit is coupled to a bit stream input terminal, and includes a timer circuit and error calculation circuitry. The timer circuit is coupled to the bit stream input terminal and a reference clock generator circuit. The error calculation circuitry is coupled to the timer circuit. The filter circuit is coupled to the measurement circuit, and includes error clipping control circuitry and clock period adjustment circuitry. The error clipping control circuitry is coupled to the error calculation circuitry. The clock period adjustment circuitry is coupled to the error calculation circuitry and the timer circuit. The frame detection circuit is coupled to the filter circuit and the bit stream input terminal.

A method of operating a communication system is disclosed. The method includes forming a data frame having plural orthogonal frequency division multiplex (OFDM) symbols. A first set of preamble subcarriers is allocated to at least one of the OFDM symbols. A second set of data subcarriers is allocated to said at least one of the OFDM symbols.