A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal to a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on analyzing the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.

An analog-to-digital converter (ADC) has been disclosed. In some implementations, the ADC is configured to generate ADC samples based on input signals and an ADC input clock. The ADC is further configured to generate at a first time point a synchronized start signal indicating a starting point of capturing the ADC samples. The start signal and a system clock can be synchronized at a second time point. At a third time point, a capturing sample clock for capturing the ADC samples is generated. The synchronized start signal and the capturing sample clock can be input to a counter to determine a time difference between the second and third time points. An ADC output timing of the ADC samples can be determined based on the time difference.

A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.

Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.

The invention relates to a peer-to-peer network having at least one first node with a first clock module and part of a peer-to-peer application. Also included is at least one second node with a second clock module and part of the peer-to-peer application. At least one communication connection between the first node and the second node is establishable. The first node comprises at least one first synchronization clock module. The second node comprises at least one second synchronization clock module. At least the first synchronization clock module is configured to transmit at least one first synchronization clock message to the second synchronization clock module via the communication connection, the second synchronization clock module is configured to synchronize the clock signal of the second clock module to the clock signal of the first clock module based on synchronization information included in the first synchronization clock message.

A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

A device, system, and method synchronizes time partition windows. The method performed at a first electronic device includes receiving a clock signal from a second electronic device, the clock signal indicating a modification to synchronize a first clock of the first electronic device to a second clock of the second electronic device. The method includes generating an operating system tick interrupt based on the clock signal, the operating system tick interrupt indicating a modification to synchronize a first operating system tick of the first electronic device to a second operating system tick of the second electronic device. The method includes generating a first schedule of first time partition windows based on the first operating system tick. The first schedule of the first time partition windows is synchronized to a second schedule of second time partition windows of the second electronic device.

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Methods, system, nodes and computer program for transmission of a synchronous data stream having a bitrate, over an asynchronous packet data network between a transmitter node and a receiver node comprising: packaging, by the transmitter node, the synchronous data stream into data packets, transmitting, by the transmitter node, the data packets onto the asynchronous packet data network with a fixed packet rate defined by a first clock frequency which corresponds to the average distance in time between two consecutive data packets transmitted onto the asynchronous packet data network, which is independent of the bitrate of the synchronous data stream, receiving, by the receiver node, the data packets from the asynchronous packet data network detecting, by the receiver node, the fixed packet rate, and based on the fixed packet rate, regenerating, by the receiver node, the first clock frequency by detection of the distance in time between two consecutive data packets received from the asynchronous packet data network.

A semiconductor apparatus includes a transmission device and a receiving device. The transmission device generates an output signal from a transmission signal in synchronization with a clock signal. The receiving device generates a reception signal from the output signal in synchronization with the clock signal and a delayed clock signal generated by delaying the clock signal by a preset time, based on an operating speed of the semiconductor apparatus.