A signal receiving apparatus includes a clock and data recovery (CDR) circuit, a first sampler, and at least one deskew circuit. The CDR circuit receives a first signal through a first lane of the signal receiving apparatus and decodes the first signal to extract a first clock signal from the first signal. The CDR circuit provides the first clock signal to the first sampler and the least one deskew circuit. The first sampler receives the first signal through the first lane of the signal receiving apparatus. The first sampler samples the first signal based on the first clock signal to generate a first output signal. The at least one deskew circuit receives a second signal through at least one second lane of the signal receiving apparatus and adjusts a phase skew between the first clock signal and the second signal so as to generate a second output signal.

Embodiments of this application provide a method for obtaining a phase detection signal in a clock recovery circuit and a phase detector, configured to obtain a correct phase detection signal. A phase detector obtains sampling sequences sent by an analog to digital converter ADC, where the sampling sequences are obtained by the ADC by sampling, an electrical signal received by the ADC, and the electrical signal carries a pre-configured training sequence; the phase detector calculates a correlation between the sampling sequences and a comparison sequence, to determine a first location and a second location, where the first location and the second location are locations of a starting point of the training sequence in the sampling sequences; and the phase detector obtains a phase detection signal based on a difference parameter of the first location and the second location.

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

An integrated circuit is operable in two modes, including a test mode in which a pattern of variation is injected into a receiver's sampling clock and used to simulate jitter. Adding frequency offset, jitter or both, to this clock can be equivalent to adding jitter of an equal magnitude but opposite sign in a transmitted test signal. In this way, a clock can be produced that simulates timing variations that can be encountered during mission function operation of the device under test, while test input data is applied by local pattern generators or other data sources that, under test conditions, do not, or need not, exhibit such variations. In detailed embodiments, these techniques can be separately employed in one or more clock and data recovery circuits (CDRs) of the integrated circuit; for example, a first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input.

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

System and method of frame alignment at a receiver with power optimization mechanisms. A framer is configured to perform a frame alignment process on a data stream and enter an inactive state after frame alignment is achieved. In the inactive state, the circuits used to perform the frame alignment process in the framer can be powered down or otherwise placed in a power reduction mode. Responsive to an indication that data processing at the receiver becomes out-of-frame again, the framer can wake up from the inactive state and restart the frame alignment process. An out-of-frame indication may be generated by error detection logic (e.g., forward error correction (FEC) decoder) when it detects an excessive number of uncorrectable errors.

In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI.

An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

An electronic device includes a receiver circuit, a clock generator circuit, and a clock control circuit. The receiver circuit receives first clock information associated with a first clock of another electronic device. The clock generator circuit generates a second clock for the electronic device. The clock control circuit obtains second clock information associated with the second clock, generates a clock control signal according to the first clock information and the second clock information, and outputs the clock control signal to the clock generator circuit, where the clock generator circuit adjusts the second clock in response to the clock control signal.