An electronic device includes: a first semiconductor device having a plurality of transmitting units; a second semiconductor device having a plurality of receiving units; and a plurality of wirings coupling between the plurality of transmitting units and the plurality of receiving units and also transmitting a data signal from the plurality of transmitting units to the plurality of receiving units. Here, the plurality of wirings has: a plurality of first wirings each having a signal delay that is divisible by a half of a time of the data signal; and a plurality of second wirings each having a signal delay that is not divisible by the half of the time of the data signal. The plurality of first wirings is arranged at a first wiring interval. Also, the plurality of second wirings is arranged at a second wiring interval wider than the first wiring interval.

An analog-to-digital converter (ADC) has been disclosed. In some implementations, the ADC is configured to generate ADC samples based on input signals and an ADC input clock. The ADC is further configured to generate at a first time point a synchronized start signal indicating a starting point of capturing the ADC samples. The start signal and a system clock can be synchronized at a second time point. At a third time point, a capturing sample clock for capturing the ADC samples is generated. The synchronized start signal and the capturing sample clock can be input to a counter to determine a time difference between the second and third time points. An ADC output timing of the ADC samples can be determined based on the time difference.

An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

The present disclosure includes a time-to-digital converter (TDC) based RF-to-digital (RDC) data converter for time domain signal processing polar receivers. Polar data conversion achieves better SNR tolerance owing to its phase convergence near the origin in a polar coordinate. The proposed RDC consists of a TDC for phase detection and an analog-to-digital converter (ADC) for amplitude conversion. Unlike the conversional data converter, the proposed ADC's sampling position is guided by the detected phase result from the TDC's output. This TDC assisted data-converter architecture reduces the number of bits required for the ADC. In addition, oversampling is no longer needed. With precisely controlled tunable delay cells and gain compensator, this hybrid data convertor is capable to directly convert Quadrature Amplitude Modulation (QAM) waveforms and Amplitude Phase Shift Keying (APSK) waveforms directly from the RF signal without down-conversion. Thus, the proposed RDC architecture achieves lower power consumption and better performance comparing with conventional I/Q receivers.

The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.

A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.

A method of synchronising a communication signal entering into a receiver. Each frame of the signal includes a learning symbol formed of N repetitions of a learning sequence. The method includes the determination of a total correlation signal by correlating the input signal with a correlation symbol formed of N repetitions of a correlation sequence corresponding to all or part of the learning sequence and duration t.sub.sc, and the determination of a partial correlation signal by correlating the input signal with the correlation sequence. A peak of the total correlation signal is identified at an instant t.sub.pct. At least one threshold is defined from the power of the peak of the total correlation signal, and the power of the partial correlation signal is compared here to the instants t.sub.pctk*t.sub.sc, with k a whole number between 0 and N1.

A positioning measurement device is provided. The device includes a light source, a grating, and plural light sensors. A periodic light field is generated by light emitted by the light source and passes through the grating to. The plural light sensors are periodically spaced. The light sensors are used to sense the periodic light field for generating a plurality of positioning measurement signals.

The invention relates to a peer-to-peer network having at least one first node with a first clock module and part of a peer-to-peer application. Also included is at least one second node with a second clock module and part of the peer-to-peer application. At least one communication connection between the first node and the second node is establishable. The first node comprises at least one first synchronization clock module. The second node comprises at least one second synchronization clock module. At least the first synchronization clock module is configured to transmit at least one first synchronization clock message to the second synchronization clock module via the communication connection, the second synchronization clock module is configured to synchronize the clock signal of the second clock module to the clock signal of the first clock module based on synchronization information included in the first synchronization clock message.