A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented fast turn-on bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

The present disclosure is directed to systems and methods for communicating between rack mounted devices disposed in the same or different racks separated by distances of less than a meter to a few tens of meters. The system includes a CMOS first mm-wave engine that includes mm-wave transceiver circuitry, mm-wave MODEM circuitry, power distribution and control circuitry, and a mm-wave waveguide connector. The CMOS first mm-wave engine communicably couples to a CMOS second mm-wave engine that also includes mm-wave transceiver circuitry, mm-wave MODEM circuitry, power distribution and control circuitry, and a mm-wave waveguide connector. In some implementations, at least a portion of the mm-wave transceiver circuitry may be fabricated using III-V semiconductor manufacturing methods. The use of mm-wave communication techniques beneficially improves data integrity and increases achievable datarates, and reduces power costs.

A signal processing device for a receiver includes: a descrambler, descrambling an input signal to generate a descrambled signal; a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal; an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; and a decoder, decoding the equalized signal to obtain data included in the input signal.

A device (1)) with an antenna that receives a target carrier signal (3) from a remote target (2) and transmits a device carrier signal (6) modulated with data to communicate data between the device (1) and the target (2), which device (1) comprises: clock extraction means (4) to extract a target clock (5) from the target carrier signal (3); driver means (9) to generate the device carrier signal (6) from a device clock (8); synchronization means (7) to synchronize the frequency and phase of the device clock (8) with the target clock (5), wherein that the synchronization means (7) comprise: time measurement means (10) to measure the phase difference between the target clock (5) and the device clock (8) or an internal device clock (33) related to the device clock (8) and to provide a phase information (1,2,3); measurement control means (20) to initiate a first time measurement that results in a first phase information () and to initiate a second time measurement a fixed time period (T) after the first time measurement that results in a second phase information (2); frequency correction means (11) to correct the frequency of the device clock (8) and/or the internal device clock (33) to the frequency of the target clock (5) based on an evaluation of the first phase information () and second phase information (2) by evaluation means (21); which measurement control means (20) are built to initiate a third time measurement after the frequency correction of the device clock (8) and/or the internal device clock (33) that results in a third phase information (3) evaluated by the evaluation means (21) and corrected by phase correction means (22) which correct the phase of the device clock (8) to the phase of the target clock (5).

In an optical communications system, the thermal pathway for dissipating heat generated by clock and data recovery (CDR) circuitry of an optical communications module is a separate from the thermal pathway that is used to dissipate heat generated by other components of the module. The CDR circuitry is external to the module and is provided with its own heat dissipation device. Keeping the CDR circuitry external to the module and providing it with its own heat dissipation device decouples the thermal pathway for dissipating heat generated by the CDR circuitry from the thermal pathways used for dissipating heat generated by other components of the module. This results in more effective heat dissipation and better component performance.

Various embodiments include apparatus and methods having a data receiver with a real time clock decoding decision feedback equalizer. In various embodiments, a digital decision feedback loop can be implemented in a data receiver circuit, while all analog signals involved are static relative to the input signal data rate. The implemented data receiver circuit can include a number of data latches with different, but static, analog unbalances and a decision-based clock decoder. In an example, the analog unbalances may be different reference voltages. The decision-based clock decoder can be structured to activate only one data latch, the one with the desired analog unbalance. The outputs of the latches attached to the same clock decoder can be combined such that only the active latch drives the final output. Additional apparatus, systems, and methods are disclosed.

One example includes a master microcontroller in a communication interface system. The microcontroller includes a transmitter configured to generate a clock signal at a selected frequency and to provide the clock signal to a slave microcontroller on a two-wire communication cable during a clock learning mode. The transmitter can be further configured to provide master data signal requests at the selected frequency on the two-wire communication cable during a data transfer mode. The microcontroller also includes a receiver configured to receive slave data signals at the variable frequency via the two-wire communication cable in response to the master data signal requests during the data transfer mode.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.