In a self-synchronous transmission scheme, received data is accurately acquired. A timing signal generating unit generates timing signals indicating different timings in synchronization with a timing at which a status of a reception signal transitions. A first data signal generating unit generates a first data signal from statuses of the reception signal before and after a timing at which a predetermined first timing signal becomes a specific value, and outputs the first data signal in synchronization with a second timing signal different from the first timing signal. A second data signal generating unit generates a second data signal from statuses of the reception signal before and after a timing at which the second timing signal becomes the specific value, and outputs the second data signal in synchronization with a timing signal different from the first timing signal.

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

A method and system for synchronising a server cluster having a plurality of nodes each provided with an internal clock and interconnected with each other by a clock interconnection network including a plurality of transmission segments. Time-stamping information is generated by the internal clock of a source chosen from the nodes of the server cluster. The time-stamping information is transmitted to all the nodes in the server cluster from the source; and the internal clock of each node of the server cluster is adjusted from this time stamping information. The time for transmission of the time-stamping information is adjusted by each transmission segment to a constant value established for each transmission segment. Upon receiving the time-stamping information by any one of the nodes in the server cluster, its internal clock is adjusted from the time-stamping information and information relating to the transmission segments passed through between the source and this node.

A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n?1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n?1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n?1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n?1 first signals transitions from the second signal level to the first signal level, to output n?1 second signals.

In some aspects, the disclosure is directed to methods and systems for synchronized multi-client content delivery, and a content selection system based on individual and aggregated scores for the content items, to generate bundles or sets of content items having approximately corresponding scores. Server timers and local timers on client devices may be synchronized via notifications, and timer durations dynamically adjusted when client requests and responses are sent prior to client-side timer expiration, but received after server-side timer expiration, indicating communication latency has caused desynchronization. Timers may be adjusted on a global basis or per-client device basis. Through scoring and bundling, sets of content items that may be relevant to approximately an equal share of the recipient client devices may be selected and transmitted.

A receiver includes: a PHY layer, and a processor coupled to the PHY layer. The processor is configured to: receive a set of data bits from the PHY layer; compare the set of data bits to a sync header pattern; determine a mismatch metric responsive to the comparison and to an adjustable scaling factor, and execute link synchronization operations based on the mismatch metric.

A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.

Example disposable biosensor devices having an activity sensor are disclosed. One example device includes a disposable biosensor that has a first electrode having a distal end to be inserted into a subcutaneous layer beneath a person's skin, the first electrode having a reactive material disposed on the distal end, and a second electrode. The disposable biosensor device also includes an activity sensor that can be activated upon an activity by the person, the activity sensor for detecting the activity and providing data about the activity. The disposable biosensor also includes a radio frequency transmitter for transmitting data obtained from the first or second electrode and the activity sensor.

A method and system for duty-cycled high speed clock and data recovery with forward error correction are provided. The system operates on a first digital signal comprising a first plurality of samples and a second digital signal comprising a second plurality of samples. The second plurality of samples may be a subset of the first plurality of samples, for example, if the first and second pluralities of samples are generated by one analog-to-digital converter. A clock and data recovery module is operable to produce a timing indication according the second digital signal. The second plurality of samples is sampled intermittently. The discontinuity between bursts of samples in the second signal corresponds to a duty cycle. A forward error correction module is operable to produce a digital error-corrected signal according to the first digital signal and the timing indication.

System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the FAW in the incoming data, with each comparator configured to serially compare multiple windows of a parallel M-bit block (as provided from a parallel data bus) with the FAW. Multiple comparators in the framer may operate in parallel to search for the FAW at different windows. This configuration can significantly reduce the comparator count and so the gate count as well as the chip area in a framer. Power consumption can be advantageously reduced as one comparator operating serially consumes less power than multiple comparators in parallel because less gate toggling is involved.