An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

An optical receiver adapted to convert a received optical signal into a phase change of a timing signal to generate a first modified timing signal and to generate a data signal by comparing the first modified timing signal with a reference signal.

A device comprises a clock data recovery (CDR) circuit. The CDR circuit has an input node to receive an input data signal, an output node, a data recovery circuit, and a self-test circuit. The CDR circuit supports a first mode of operation and a second mode of operation. In the first mode, the CDR circuit receives the input data signal at the input node and provides the input data signal to an input of the data recovery circuit, the data recovery circuit recovers first data from the input data signal, and the CDR circuit provides the first data for output at the output node. In the second mode, the self-test circuit generates a test data pattern which is provided to the output node and looped back to the input of the data recovery circuit, the data recovery circuit recovers second data from the test data pattern, and the self-test circuit checks the second data for errors.

The present disclosure is directed to systems and methods for communicating between rack mounted devices disposed in the same or different racks separated by distances of less than a meter to a few tens of meters. The system includes a CMOS first mm-wave engine that includes mm-wave transceiver circuitry, mm-wave MODEM circuitry, power distribution and control circuitry, and a mm-wave waveguide connector. The CMOS first mm-wave engine communicably couples to a CMOS second mm-wave engine that also includes mm-wave transceiver circuitry, mm-wave MODEM circuitry, power distribution and control circuitry, and a mm-wave waveguide connector. In some implementations, at least a portion of the mm-wave transceiver circuitry may be fabricated using III-V semiconductor manufacturing methods. The use of mm-wave communication techniques beneficially improves data integrity and increases achievable datarates, and reduces power costs.

Various embodiments include apparatus and methods having a data receiver with a real time clock decoding decision feedback equalizer. In various embodiments, a digital decision feedback loop can be implemented in a data receiver circuit, while all analog signals involved are static relative to the input signal data rate. The implemented data receiver circuit can include a number of data latches with different, but static, analog unbalances and a decision-based clock decoder. In an example, the analog unbalances may be different reference voltages. The decision-based clock decoder can be structured to activate only one data latch, the one with the desired analog unbalance. The outputs of the latches attached to the same clock decoder can be combined such that only the active latch drives the final output. Additional apparatus, systems, and methods are disclosed.

A system for generating a self-receive signal includes: a signal generator; a first signal processor; a second signal processor; and an antenna. The system also includes a first passive coupling device: defining a first input port electromagnetically coupled to the signal generator; defining a first transmitted port; defining a first coupled port electromagnetically coupled to the first signal processor; and characterized by a first phase balance between the first transmitted port and the first coupled port. The system further includes a second passive coupling device: defining a second input port electromagnetically coupled to the antenna; defining a second transmitted port electromagnetically coupled to the first transmitted port; defining a second coupled port electromagnetically coupled to the second signal processor; and characterized by a second phase balance between the second transmitted port and the second coupled port substantially similar to the first phase balance.

A falling-edge modulation signal receiver is configured to process an input signal having a duty cycle varying with a bit value of the input signal. The receiver includes: a phase-locked loop for generating an oversampling clock according to the input signal which correlates with a signal clock, wherein the oversampling frequency is not lower than five times the frequency of the signal clock; an oversampling circuit for sampling the input signal according to the oversampling clock and thereby generating multiple groups of data which as a whole is corresponding to a single bit of the input signal; and a decision circuit for ascertaining that X bits of the multiple groups of data are 1 and determining the value of the single bit according to the X. When the X is greater/less than a threshold, the decision circuit determines that the value of the single bit is 1/0.

A signal processing apparatus includes: an autocorrelation processing circuit configured to generate an autocorrelation symbol; a symbol replica generation circuit configured to generate a symbol replica; an individual likelihood value calculation circuit configured to calculate a plurality of individual likelihood values by using the generated autocorrelation symbol and the generated symbol replica; a path likelihood value calculation circuit configured to integrate, for each of the plurality of calculated individual likelihood values, the individual likelihood value of the target frame and an integrated value of an individual likelihood value of a frame preceding the target frame to obtain a plurality of path likelihood values; and a path likelihood value selection circuit configured to select the largest path likelihood value from among the calculated path likelihood values to output frame identification information that corresponds to the selected path likelihood value.

Systems and methods for extracting and identifying timing information from wireless signals can include a signal receiver configured to receive a communications signal; a finite impulse response (FIR) filter coupled to the signal receiver and configured to identify a set of transitions in the communications signal; an absolute value operation module coupled to the FIR filter and configured to detect energy in each of the set of transitions within the communications signal; and a comb filter coupled to the absolute value operation module and configured to combine the detected energy in each of the set of transitions within the communications signal. Exemplary systems can also include a cyclic accumulator coupled to the comb filter and a signal processor.

A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.