Method and system for providing data monitoring and management including RF communication link over which a transmitter and a receiver is configured to communicate, the transmitter configured to periodically transmit a data packet associated with a detected analyte level received from an analyte sensor, and the receiver configured to identify the transmitter as the correct transmitter for which it is configured to receive the data packets, and to continue to receive the data packets from the transmitter once the transmitter identification has been verified, is provided.

A method and system for synchronizing a server cluster having a plurality of nodes each provided with an internal clock and interconnected with each other by a clock interconnection network comprising a plurality of transmission segments. Time-stamping information is generated by the internal clock of a source chosen from the nodes of the server cluster. The time-stamping information is transmitted to all the nodes in the server cluster from the source; and and the internal clock of each node of the server cluster is adjusted from this time-stamping information The time for transmission of the time-stamping information is adjusted by each transmission segment to a constant value established for each transmission segment. Upon receiving the time-stamping information by any one of the nodes in the server cluster, its internal clock is adjusted from the time-stamping information and information relating to the transmission segments passed through between the source and this node.

A 100BASE-TX transceiver includes a receive (RX) circuit, a transmit (TX) circuit, a clock generator circuit, a clock and data recovery (CDR) circuit, and a clock multiplexer circuit. The RX circuit receives an input data to generate an RX data. The TX circuit transmits a TX data according to a TX clock, to generate an output data. The clock generator circuit generates an output clock. The CDR circuit generates an RX recovered clock according to the RX data. The clock multiplexer circuit receives the output clock and the RX recovered clock, and outputs the TX clock that is selected from the output clock and the RX recovered clock.

A method and apparatus according to the present invention addresses and/or prevents lost protocol synchronization in HARQ systems caused by ACK/NACK errors. One embodiment detects lost synchronization errors for NDI-based retransmission protocols and restores synchronization by sending an explicit RESET message. In response to the RESET message, the transmitter aborts the transmission of a current PDU and transmits a new PDU and corresponding NDI. Another embodiment prevents protocol synchronization errors by sending scheduling grants on a packet by packet basis. The receiver sends a subsequent explicit scheduling grant to the transmitter based on an error evaluation of a received PDU. The transmitter will not send the next PDU unless it receives the subsequent explicit scheduling grant.

A system for generating a self-receive signal includes: a signal generator; a first signal processor; a second signal processor; and an antenna. The system also includes a first passive coupling device: defining a first input port electromagnetically coupled to the signal generator; defining a first transmitted port; defining a first coupled port electromagnetically coupled to the first signal processor; and characterized by a first phase balance between the first transmitted port and the first coupled port. The system further includes a second passive coupling device: defining a second input port electromagnetically coupled to the antenna; defining a second transmitted port electromagnetically coupled to the first transmitted port; defining a second coupled port electromagnetically coupled to the second signal processor; and characterized by a second phase balance between the second transmitted port and the second coupled port substantially similar to the first phase balance.

Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

An Ethernet physical layer circuit and a clock recovery method are provided. An analog-to-digital converter samples an analog input signal with a sampling clock to generate a digital input signal. A clock generator is coupled to the analog-to-digital converter, outputs the sampling clock to the analog-to-digital converter, and adjusts a phase of the sampling clock according to a phase control signal. The clock recovery circuit is coupled to the analog-to-digital converter and the clock generator, detects a timing error of the digital input signal at refresh stages in a lower energy consumption idle mode to obtain phase adjustment information, and generates the phase control signal based on the phase adjustment information at quiet stages in the low power idle mode. The clock generator correspondingly receives the phase control signal in the quiet stages to adjust the phase of the sampling clock.

An anti-aliasing channel estimation apparatus and method and a receiver where the anti-aliasing channel estimation method includes: performing clock recovery and data synchronization on a received multicarrier signal with channel aliasing, to obtain a synchronized time-domain signal and a sampling phase; calculating an estimation signal after passing through a channel and being aliased based on a training sequence and the sampling phase, and obtaining a channel response and an aliasing signal response of each subcarrier of the multicarrier signal based on the estimation signal and the frequency-domain signal. Therefore, channel estimation may be performed on the multicarrier signal with channel aliasing, influence of the channel aliasing on the bit error rate may be lowered, and transmission quality of the system may be improved.

Methods and systems are described for generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal, generating a phase-error signal using a phase comparator receive a phase of the local clock signal and a reference clock signal, and configured to output the phase-error signal, generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal, and generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal.