Methods and systems are described for generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal, generating a phase-error signal using a phase comparator receive a phase of the local clock signal and a reference clock signal, and configured to output the phase-error signal, generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal, and generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal.

A radio communication device has an analog control loop unit to generate an analog control signal, a digital control loop unit which has a frequency determined with the frequency of a reference signal and a predetermined frequency setting code signal, a voltage controlled oscillator to generate the voltage control oscillation signal, a data slicer to generate a digital signal obtained by digitally demodulating the reception signal, an automatic offset controller to generate a correction signal, a setting code adjuster to adjust the frequency setting code signal, based on the correction signal, and a direct-current level adjuster to adjust a direct-current level of the digital control signal, based on the correction signal. The data slicer compares the digital control signal adjusted by the direct-current level adjuster, with the threshold value.

An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

Methods and systems are described for generating, using a voltage-controlled oscillator (VCO), a plurality of phases of a local clock signal, generating a phase-error signal using a phase comparator receive a phase of the local clock signal and a reference clock signal, and configured to output the phase-error signal, generating a frequency-lock assist (FLA) signal using a FLA circuit receiving one or more phases of the local clock signal and the reference clock signal, the FLA signal indicative of a magnitude of a frequency error between the reference clock signal and the local clock signal, and generating a VCO control signal using an error accumulator circuit receiving the phase-error signal and the FLA signal, and responsively providing the VCO control signal to the VCO to lock the local clock signal to the reference clock signal.

A method for long-term evolution (LTE) synchronization by a signal receiver in the presence of interference signals including providing multiple parallel adaptive filters to eliminate the contribution of an interference signal to a timing metric of an LTE signal; wherein coefficients of each of the parallel adaptive filters are determined using a linearly constrained minimum variance (LCMV) criterion to minimize output power of each filter subject to the LCMV criterion that preserves received signal vectors corresponding to all possible primary synchronization signal signatures; and wherein the LCMV criterion are updated iteratively using a recursive least squares (RLS) algorithm.

In a self-synchronous transmission scheme, received data is accurately acquired. A timing signal generating unit generates timing signals indicating different timings in synchronization with a timing at which a status of a reception signal transitions. A first data signal generating unit generates a first data signal from statuses of the reception signal before and after a timing at which a predetermined first timing signal becomes a specific value, and outputs the first data signal in synchronization with a second timing signal different from the first timing signal. A second data signal generating unit generates a second data signal from statuses of the reception signal before and after a timing at which the second timing signal becomes the specific value, and outputs the second data signal in synchronization with a timing signal different from the first timing signal.

A data communication framing scheme of a bit stream that is divided among a plurality of discrete physical frames, each physical frame is of a definite number of symbols in duration, each symbol is associated with at least one sub-carrier in a plurality of sub-carriers, the physical frame is partitioned in time into at least an uplink zone and a downlink zone, the data framing scheme comprising a logical frame having a logical frame start position that is offset by a rational number of said symbols from a reference symbol, said reference symbol is selected from said definite number of symbols, wherein said logical frame extends in time to coincide with at least part of the duration of said physical frame and at least part of the duration of another physical frame in said plurality of discrete physical frames.

In general, the disclosure describes techniques for communicating multicast group leave requests between two or more load-balanced, multi-homed PE routers included in an Ethernet Virtual Private Network (EVPN). The techniques of the disclosure enable the two or more PE routers to synchronize IGMP state and routing information amongst one another to ensure that the one of the multi-homed PE routers elected as the designated forwarder (DF) ceases forwarding the multicast group traffic to the CE router, even if it is not the PE router that receives the IGMP leave request.

The invention relates to a device for the radio transmission of a data word between a transmitter (1) and a receiver (65), comprising a transmitter (1) that can transmit at least one block of data comprising a preamble word and a data word repeated several times; an elementary synchronization block allowing the synchronization of the receiver (65) to the transmitter (1) and the detection of the preamble word; and a synchronous averaging device (67) calculating the average of the data word repeated.

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.