A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.

A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.

Component signal values are derived from component signals and fed to at least one fixed equalizer which generates equalizer output signals. The signals are fed to phase error detectors generating phase error signals. The phase error signals are combined with further phase error signals derived by further error detectors receiving signal values from further equalizers and/or the component signal values directly from sample units.

A decoding device for an absolute positioning code is provided. The decoding device includes a linear feedback shift register (LFSR), a lookup table (LUT) circuit, a counter circuit, and a computation circuit. The LFSR includes n registers, for loading the absolute positioning code with a first frequency. The LFSR performs shifting operation according to a clock signal having a second frequency greater than or equal to the first frequency. The LUT circuit outputs a lookup result and a valid flag according to values stored in the n registers. The lookup result has k different data, k(2.sup.n1). The counter circuit resets according to the valid flag, and performs counting operation according to the clock signal to generate a counting result. The computation circuit performs calculation according to the lookup result and the counting result to generate a decoding result when the valid flag indicates valid.

Provided is a method for mitigating, by an interference mitigation apparatus, interference on a home network transmission line. The method includes pairing domain masters with relay terminals by a signal having a unique frequency, grouping the domain masters, performing Tx/Rx synchronization between the domain masters and the relay terminals, and controlling the domain masters and the relay terminals to transmit/receive data according to the Tx/Rx synchronization. The domain masters of the same groups may be controlled not to simultaneously transmit/receive data.

A clock recovery circuit includes an oscillator to generate a clock signal. The oscillator varies a frequency of the clock signal as a function of a control signal. The clock recovery circuit has a phase tracking control loop to determine the phase error between the reference signal and the clock signal, and vary the control signal as a function of the phase error. The phase tracking control loop has a linear region for phase errors in the range between and +, thereby creating a cycle slippage event when the phase error exceed said range. The clock recovery circuit includes a cycle-slippage detector which determines whether the phase error reaches or approaches + or . In case the phase error reaches or approaches + or , the cycle-slippage detector acts on the control signal in an effort to avoid that said phase tracking control loop leaves said linear region.

A computer-implemented method for receiving data. Data are received in a bit stream asynchronously and serially via a transmission medium, wherein the data are received in frames that include a respective portion of the data, wherein the frames include a respective synchronization bit, wherein consecutively received frames have alternating values of the synchronization bits. A start of the consecutive frames is determined depending on the values of the bits of the frames. The portions of the data from consecutive frames are compiled without the synchronization bit to form the data. A computer-implemented method for transmitting data, a device, and a computer-implemented method for transmitting the data, are also described.

Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.

In some aspects, the disclosure is directed to methods and systems for synchronized multi-client content delivery, and a content selection system based on individual and aggregated scores for the content items, to generate bundles or sets of content items having approximately corresponding scores. Server timers and local timers on client devices may be synchronized via notifications, and timer durations dynamically adjusted when client requests and responses are sent prior to client-side timer expiration, but received after server-side timer expiration, indicating communication latency has caused desynchronization. Timers may be adjusted on a global basis or per-client device basis. Through scoring and bundling, sets of content items that may be relevant to approximately an equal share of the recipient client devices may be selected and transmitted.

Systems and methods are provided for processing data streams. The system includes at least one data source for transmitting a data stream to a data transmission network; at least one specific purpose processor in communication with the data transmission network, wherein the specific purpose processor is configured to provide a specific data processing operation; a controller coupled the data transmission network, the controller configured to: determine that the data stream requires processing according to a data processing operation; identify a data processing configuration corresponding to the data processing operation; and route the data stream to the at least one specific purpose processor.