A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.

A phase-shifter circuit arranged to receive a reference timing signal and to output a phase-shifted form of the reference timing signal. The phase-shifter circuit comprises a delay circuit arranged to receive the reference timing signal and a delay control signal, and to delay transitions within the reference timing signal to generate the phase-shifted form of the reference timing signal, wherein the amount of delay applied by the delay circuit to the transitions within the reference timing signal is controllable by the delay control signal. The phase-shifter circuit further comprises a delay control circuit arranged to receive a re-timed signal comprising transitions re-timed to transitions of the phase-shifted form of the reference timing signal output by the phase-shifter circuit, and to generate the delay control signal for the delay circuit based on the received re-timed signal.

Processing a digital bit stream and systems for implementing the methods are provided. The method includes dividing the digital bit stream into a plurality of data packets. In a first processing block performing a carrier recovery error calculation on a first portion of the plurality of data packets, comprising preforming a first phase locked loop (PLL) function on decimated data of the data packets and performing a carrier recovery operation on the first portion of the plurality of data packets. In a second processing block, in parallel with the processing of the first portion of the plurality of packets, performing the carrier recovery error calculation on a second portion of the plurality of data packets, comprising preforming the first PLL function on decimated data of the data packets and performing the carrier recovery operation on second portion of the plurality of data packets.

Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.

In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

A data reception device includes: an equalizer circuit that shapes a waveform of an input signal according to a set gain value; a CDR circuit which recovers a plurality of clock signals having different phases in one cycle from the input signal after being subjected to the waveform shaping performed by the equalizer circuit; an oversampler which performs sampling of the waveform-shaped input signal in synchronization with the plurality of clock signals and recovers a plurality of input data from the waveform-shaped input signal; and a calibration control unit which determines whether the oversampler correctly recovers the input data based on a result of the sampling performed by the oversampler, and generates a control signal to set the gain value of the equalizer circuit based on a determination result when it is determined that the input data is not correctly recovered.

A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n-1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n-1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n-1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n-1 first signals transitions from the second signal level to the first signal level, to output n-1 second signals.

A decoding device for an absolute positioning code is provided. The decoding device includes a linear feedback shift register (LFSR), a lookup table (LUT) circuit, a counter circuit, and a computation circuit. The LFSR includes n registers, for loading the absolute positioning code with a first frequency. The LFSR performs shifting operation according to a clock signal having a second frequency greater than or equal to the first frequency. The LUT circuit outputs a lookup result and a valid flag according to values stored in the n registers. The lookup result has k different data, k≦(2.sup.n−1). The counter circuit resets according to the valid flag, and performs counting operation according to the clock signal to generate a counting result. The computation circuit performs calculation according to the lookup result and the counting result to generate a decoding result when the valid flag indicates valid.

A receiver circuit includes data lane modules, a clock lane module, a bias current controller and a link layer. Each of the data lane modules receive respective data signals. The clock lane module receives clock signals and provides each of the data lane modules with a respective divided clock signal among divided clock signals. The bias current controller controls a clock bias current. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module, based on low power data signals low power clock signals. The bias current controller, based on the bias control signal, provides the clock bias current having a first magnitude to the clock lane module in a second power mode and provides the clock bias current having a second magnitude to the clock lane module in a third power mode.