A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

Phase synthesis techniques (PST) useful in a wide variety of communication systems based on wireless, optical and wireline links, disclose methods and circuits for a programmable synthesis of a waveform from a referencing clock with phase resolution matching a single gate delay.

A method of processing a digital radio broadcast signal in a digital radio receiver includes: receiving baseband signal samples at a first sample rate; adjusting the sample rate of the baseband signals based on a difference between a receiver clock and a transmitter clock to produce adjusted baseband signal samples at a second sample rate; filtering the adjusted baseband signal samples to separate a digital component of the samples and an analog component of the samples, wherein the digital component and the analog component are synchronous; and separately demodulating the digital component and the analog component to produce a digital output signal and an analog output signal. A receiver that uses the method is also provided.

A technical solution is directed to a clock recovery apparatus for multi-level signaling on a single-lane communication interface. The apparatus can use bin-map logic to successfully recover a common clock per symbol received on the multi-level signal interface. The multi-level signal can be PAM4 signaling where two bits are encoded to represent four levels. The clock recovery apparatus can detect signal level through individual edge detectors for each of the two bits and can handle jitter up to half-clock period.

A positioning measurement device is provided. The device includes a light source, a grating, and plural light sensors. A periodic light field is generated by light emitted by the light source and passes through the grating to. The plural light sensors are periodically spaced. The light sensors are used to sense the periodic light field for generating a plurality of positioning measurement signals.

This application presents an adaptive data recovery from distorted signals (ADRDS) of original data symbols from intervals or parameters of tone signals derived from a received OFDM signal, including responding to dynamic distortions introduced to the received OFDM signal by an OFDM transmission channel. Such ADRDS is implemented by converting back the derived intervals or parameters into original data symbols corresponding to distinctive sets of the intervals or parameters which the derived intervals or parameters belong to.

A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.

A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.

Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.