A method for processing a radio signal includes producing first and second streams of audio samples; decimating the first and second streams of audio samples to produce first and second streams of decimated streams of audio samples; estimating a first offset value between corresponding samples in the first and second streams of decimated streams of audio samples; shifting one of the first and second streams of audio samples by a first shift value; decimating the first and second streams of audio samples to produce third and fourth streams of decimated audio samples; estimating a second offset value; determining a final offset value based on an intersection of ranges of valid results of the first and second offset values; and shifting one of the first and second streams of audio samples by the final offset value to align the first and second streams of audio samples.

A method of operating a communication system is disclosed. The method includes forming a data frame having plural orthogonal frequency division multiplex (OFDM) symbols. A first set of preamble subcarriers is allocated to at least one of the OFDM symbols. A second set of data subcarriers is allocated to said at least one of the OFDM symbols.

A method and a system for measuring an audio transmission delay are provided. Synchronization operation is performed on transmission of an original audio codebook to be tested between a transmitter and a receiver. A transmitter starts sending the original audio codebook to be tested to a receiver in response to sending start instruction information, and stops sending the original audio codebook to the receiver in response to sending end instruction information. The receiver starts capturing the original audio codebook from the transmitter in response to receiving start instruction information and stops capturing the original audio codebook from the transmitter in response to receiving end instruction information. The audio transmission delay is obtained based on a test audio codebook captured by the receiver and the original audio codebook pre-stored in the receiver.

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

A transmission apparatus includes: a first plug-in unit including: a clock generator to generate a first clock, a first frame-pulse generator to generate a first frame-pulse-signal based on the first clock; a detector to detect a phase-difference between a first phase of the first frame-pulse-signal and a second phase of a second frame-pulse-signal transmitted from other plug-in unit, and generate phase-difference information based on the phase-difference, and a first transmitter to transmit a control-signal including the phase-difference information to the other plug-in unit; and a second plug-in unit being the other plug-in unit, including: a receiver to receive the control-signal, a controller to control a phase of a second clock of the second plug-in unit, based on the phase-difference information, a second frame-pulse generator to generate the second frame-pulse-signal based on the second clock, and a second transmitter to transmit the second frame-pulse-signal to the first plug-in unit.

In order to efficiently compensate for effects of the Doppler shift, a receiving device includes a Doppler estimator that estimates a Doppler-shift frequency fdc of a received signal. A multiplier and an LPF detect the received signal based on a carrier frequency fc of the received signal and the Doppler-shift frequency fdc estimated by the Doppler estimator 11. A timing corrector corrects a timing T for extracting symbols of the received signal after detection by the LPF so as to track the Doppler shift. A symbol extractor extracts received symbols from the received signal after detection by the LPF at a timing corrected by the timing corrector. An adaptive equalizer estimates and determines symbols from the received symbols extracted by the symbol extractor.

A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

Various embodiments provide systems and methods for performing clock recovery on a received signal using a split loop architecture. A split loop timing recovery apparatus is provided comprising a first path configured for performing frequency offset tracking on a signal by adjusting a receiver clock frequency to match a remote transmitter frequency associated with the signal and a second path configured for tracking random jitter on the signal.

A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

A timing recovery system generates a sampling clock to synchronize sampling of a receiver to a symbol rate of an incoming signal. The input signal is received over an optical communication channel. The receiver generates a timing matrix representing coefficients of a timing tone detected in the input signal. The timing tone representing frequency and phase of a symbol clock of the input signal and has a non-zero timing tone energy. The receiver computes a rotation control signal based on the timing matrix that represents an amount of accumulated phase shift in the input signal relative to the sampling clock. A numerically controlled oscillator is controlled to adjust at least one of the phase and frequency of the sampling clock based on the rotation control signal.