Embodiments relate to push notification via file sharing service synchronization. A method includes establishing synchronization, at a notification service of a mobile platform server executing on a computer processor, with a client-to-server directory of a file sharing container of a client mobile device via a file sharing service. The notification service detects a notification from the client mobile device in the client-to-server directory and determines an endpoint associated with the notification and a notification transport protocol associated with the endpoint. The notification service also selects a channel plugin associated with the notification transport protocol to establish a notification channel with the endpoint and sends a notification trigger on the notification channel to the endpoint based on the notification.

Embodiments relate to push notification via file sharing service synchronization. A system includes a computer processor and a mobile platform server executable by the computer processor. The mobile platform server includes a notification service configured to establish synchronization with a client-to-server directory of a file sharing container of a client mobile device via a file sharing service. The notification service is further configured to detect a notification from the client mobile device in the client-to-server directory and to determine an endpoint associated with the notification and a notification transport protocol associated with the endpoint. The notification service is also configured to select a channel plugin associated with the notification transport protocol to establish a notification channel with the endpoint and to send a notification trigger on the notification channel to the endpoint based on the notification.

In order to efficiently compensate for effects of the Doppler shift, a receiving device includes a Doppler estimator that estimates a Doppler-shift frequency fdc of a received signal. A multiplier and an LPF detect the received signal based on a carrier frequency fc of the received signal and the Doppler-shift frequency fdc estimated by the Doppler estimator 11. A timing corrector corrects a timing T for extracting symbols of the received signal after detection by the LPF so as to track the Doppler shift. A symbol extractor extracts received symbols from the received signal after detection by the LPF at a timing corrected by the timing corrector. An adaptive equalizer estimates and determines symbols from the received symbols extracted by the symbol extractor.

A data communication framing scheme of a bit stream that is divided among a plurality of discrete physical frames, each physical frame is of a definite number of symbols in duration, each symbol is associated with at least one sub-carrier in a plurality of sub-carriers, the physical frame is partitioned in time into at least an uplink zone and a downlink zone, the data framing scheme comprising a logical frame having a logical frame start position that is offset by a rational number of said symbols from a reference symbol, said reference symbol is selected from said definite number of symbols, wherein said logical frame extends in time to coincide with at least part of the duration of said physical frame and at least part of the duration of another physical frame in said plurality of discrete physical frames.

System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.

A half-rate clock data recovery circuit includes: a voltage-controlled oscillator (VCO) for generating a data sampling clock and an edge sampling clock according to a control voltage; an adjusting circuit for dynamically controlling the VCO to adjust the phase difference between the data sampling clock and the edge sampling clock to be different from 90 degrees in multiple test periods; and a control circuit for instructing the adjusting circuit to respectively utilize different control value combinations to control the VCO in the multiple test periods, and for recording multiple recovered-signal quality indicators respectively corresponding to the multiple test periods. Afterwards, the control circuit instructs the adjusting circuit to utilize a control value combination corresponding to the best quality indicator among the multiple recovered-signal quality indicators to control the VCO.

A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.

An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

A half-rate clock data recovery circuit includes: a voltage-controlled oscillator (VCO) for generating a data sampling clock and an edge sampling clock according to a control voltage; an adjusting circuit for dynamically controlling the VCO to adjust the phase difference between the data sampling clock and the edge sampling clock to be different from 90 degrees in multiple test periods; and a control circuit for instructing the adjusting circuit to respectively utilize different control value combinations to control the VCO in the multiple test periods, and for recording multiple recovered-signal quality indicators respectively corresponding to the multiple test periods. Afterwards, the control circuit instructs the adjusting circuit to utilize a control value combination corresponding to the best quality indicator among the multiple recovered-signal quality indicators to control the VCO.

A method of operating a communication system is disclosed. The method includes forming a data frame having plural orthogonal frequency division multiplex (OFDM) symbols. A first set of preamble subcarriers is allocated to at least one of the OFDM symbols. A second set of data subcarriers is allocated to said at least one of the OFDM symbols.