A method of performing synchronization in a super regenerative receiver (SRR) includes setting a quench rate of the SRR to a value of 1.5 times a chip rate of an incoming signal, acquiring an expected preamble sequence of an arbitrary sample set among a plurality of possible sample sets, acquiring an expected start frame delimiter (SFD) sequence for all of the possible sample sets to achieve frame synchronization, computing respective correlation metrics for bits of the expected SFD sequence while the expected SFD sequence is acquired for all of the possible sample sets, calculating a decision metric based on the correlation metrics in response to an SFD sequence being detected for one or more of the possible sample sets, and identifying a best sample set for demodulating the incoming signal among all of the possible sample sets based on the decision metric to achieve pulse synchronization.

Techniques for pilot-aided carrier frequency and phase synchronization may use a three-pass process. In a first pass, initial frequency offset may be addressed, and a frame start time may be established. In a second pass, a fine frequency correction may be performed. In a third pass, phase variation may be tracked and corrected using a minimum set of pilot symbols.

An optical receiver adapted to convert a received optical signal into a phase change of a timing signal to generate a first modified timing signal and to generate a data signal by comparing the first modified timing signal with a reference signal.

A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.

A clock recovery circuit includes an oscillator to generate a clock signal. The oscillator varies a frequency of the clock signal as a function of a control signal. The clock recovery circuit has a phase tracking control loop to determine the phase error between the reference signal and the clock signal, and vary the control signal as a function of the phase error. The phase tracking control loop has a linear region for phase errors in the range between and +, thereby creating a cycle slippage event when the phase error exceed said range. The clock recovery circuit includes a cycle-slippage detector which determines whether the phase error reaches or approaches + or . In case the phase error reaches or approaches + or , the cycle-slippage detector acts on the control signal in an effort to avoid that said phase tracking control loop leaves said linear region.

Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

A transmission apparatus includes: a first plug-in unit including: a clock generator to generate a first clock, a first frame-pulse generator to generate a first frame-pulse-signal based on the first clock; a detector to detect a phase-difference between a first phase of the first frame-pulse-signal and a second phase of a second frame-pulse-signal transmitted from other plug-in unit, and generate phase-difference information based on the phase-difference, and a first transmitter to transmit a control-signal including the phase-difference information to the other plug-in unit; and a second plug-in unit being the other plug-in unit, including: a receiver to receive the control-signal, a controller to control a phase of a second clock of the second plug-in unit, based on the phase-difference information, a second frame-pulse generator to generate the second frame-pulse-signal based on the second clock, and a second transmitter to transmit the second frame-pulse-signal to the first plug-in unit.

A receiver circuit includes data lane modules, a clock lane module, a bias current controller and a link layer. Each of the data lane modules receive respective data signals. The clock lane module receives clock signals and provides each of the data lane modules with a respective divided clock signal among divided clock signals. The bias current controller controls a clock bias current. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module, based on low power data signals and low power clock signals. The bias current controller, based on the bias control signal, provides the clock bias current having a first magnitude to the clock lane module in a second power mode and provides the clock bias current having a second magnitude to the clock lane module in a third power mode.

A multichannel receiver includes multiple receiver modules, each having: a voltage-controlled oscillator that generates a clock signal with a controllable frequency; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal; a timing error estimator that operates on the digital receive signal to provide timing error estimates; a phase control filter that derives, from the timing error estimates, a phase control signal supplied to the phase interpolator, wherein the phase control signal minimizes a phase error between the sampling signal and the analog receive signal; and a frequency control filter that derives, from the timing error estimates, a frequency control signal for controlling the clock signal frequency, wherein the frequency control signal minimizes a frequency offset between the clock signal and the analog receive signal.

Described herein are methods, systems, and software for accommodating failover of a content node in a content delivery network. In one example, a method of operating a content node includes receiving a communication for an end user device from a control node, wherein an interrupted content node previously handled the communication. The method further includes determining if the communication includes a synchronization packet and identifying connection information for the communication. The method also provides, if the communication includes a synchronization packet, accepting the communication and handling delivery for the end user device. The method also includes, if the communication does not include the synchronization packet, determining if a match exists between the connection information for the communication and connection information stored in a flow table, and handling the communication based on the match.