A method of processing a digital radio broadcast signal in a digital radio receiver includes: receiving baseband signal samples at a first sample rate; adjusting the sample rate of the baseband signals based on a difference between a receiver clock and a transmitter clock to produce adjusted baseband signal samples at a second sample rate; filtering the adjusted baseband signal samples to separate a digital component of the samples and an analog component of the samples, wherein the digital component and the analog component are synchronous; and separately demodulating the digital component and the analog component to produce a digital output signal and an analog output signal. A receiver that uses the method is also provided.

The invention relates to a device for the radio transmission of a data word between a transmitter (1) and a receiver (65), comprising a transmitter (1) that can transmit at least one block of data comprising a preamble word and a data word repeated several times; an elementary synchronisation block allowing the synchronisation of the receiver (65) to the transmitter (1) and the detection of the preamble word; and a synchronous averaging device (67) calculating the average of the data word repeated.

Methods, system, nodes and computer program for transmission of a synchronous data stream having a bitrate, over an asynchronous packet data network between a transmitter node and a receiver node comprising: packaging, by the transmitter node, the synchronous data stream into data packets, transmitting, by the transmitter node, the data packets onto the asynchronous packet data network with a fixed packet rate defined by a first clock frequency which corresponds to the average distance in time between two consecutive data packets transmitted onto the asynchronous packet data network, which is independent of the bitrate of the synchronous data stream, receiving, by the receiver node, the data packets from the asynchronous packet data network detecting, by the receiver node, the fixed packet rate, and based on the fixed packet rate, regenerating, by the receiver node, the first clock frequency by detection of the distance in time between two consecutive data packets received from the asynchronous packet data network.

A Wireless Subterranean Soil Monitoring System. The system measures the complex permittivity around a subterranean antenna, and then responsively adjusts the antenna's tuning circuit according to the measured permittivity. Once tuned, the system will then execute the transmission of the probe data. Furthermore, the antenna design is adapted for subterranean use to further reduce the de-tuning effect of the adjacent soil.

A circuit for estimating a time difference between a first signal and a second signal includes a first signal line for receiving the first signal; a delay unit configured to receive the second signal and delay the second signal so as to provide a plurality of delayed versions of the second signal, each delayed version being delayed by a different amount of delay to the other delayed versions; a comparison unit configured to compare each of the delayed versions of the second signal with the first signal so as to identify which of the delayed versions of the second signal is the closest temporally matching signal to the first signal; and a difference estimator configured to estimate the time difference between the first and second signals in dependence on the identified delayed version.

A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.

Techniques, methods and system, for synchronization of sparse data signals are disclosed, comprising mixing a serial stream of sparse data signals with a serial stream of synchronization signals, to thereby add redundancy to the serial stream of sparse data signals and enable clock regeneration from a serial stream of mixed signals produced by said mixing, emulating the serial stream of synchronization signals by applying the clock regeneration to the serial stream of mixed signals, and generating a stream of parallel synchronization signals having a frequency of the serial stream of synchronization signals, deserializing the serial stream of mixed signals into a stream of parallel mixed signals having a data rate lower than a data rate of the serial signal streams, and demixing the stream of parallel synchronization signals with the stream of parallel mixed signals and thereby removing the redundancy introduced by the mixing into the sparse data signals and generating a parallel stream of demixed signals substantially synchronized with said synchronization signals.

Component signal values are derived from component signals and fed to at least one fixed equalizer which generates equalizer output signals. The signals are fed to phase error detectors generating phase error signals. The phase error signals are combined with further phase error signals derived by further error detectors receiving signal values from further equalizers and/or the component signal values directly from sample units.

The present invention is directed to data communication. More specifically, the present invention provides a mechanism for determining an adjustment delay that minimizes skew error due to poor alignment between edge samples and data samples. The adjustment delay is determined by sampling edge samples and data samples using different test delays at a calibration frequency that is different from the sampling frequency. The test delay associated with the least average position between the data samples and edge samples is selected as the adjustment delay. The adjustment delay is used as a parameter when sampling data at the sampling frequency. There are other embodiments as well.

A receiver having analog to digital converters with phase adjustable sampling clocks. A first analog to digital converter converts an analog signal into first digital samples under control of a first sampling clock. A first clock generator adjusts a phase of the first sampling clock based on at least one first phase control signal. A second analog to digital converter converts the analog signal into second digital samples under control of a second sampling clock. A second clock generator adjusts the phase of the second sampling clock based on at least one second phase control signal. A data decision circuit recovers data based on the first and second samples. Feedback circuitry receives the recovered data and generates at least one first phase control signal for the first clock generator and generates at least one second phase control signal for the second clock generator based on the first phase control signal.