A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.

Provided are a device synchronization method and apparatus, a device, and a storage medium. The device synchronization method includes: in response to determining that a second device does not receive a first data packet, determining a target time cycle for sending data packets by the second device based on a preset cycle adjustment parameter and a preset time slice length; determining whether the second device receives a second data packet sent by the first device based on the time slice length and the target time cycle of the second device; and in response to determining that the second device receives the second data packet sent by the first device, determining a time point for sending a data packet next time by the second device according to data packet information of the first device, achieving cycle synchronization of the second device in a preset synchronization cycle time period.

A time synchronization system includes time masters and a management master. The management master includes a management master priority requester that transmits to each time master a priority request frame and a management master highest priority processor that transmits, to a time master holding a priority that is the highest among priorities of the time masters, a highest priority notification frame for changing the priority to the highest priority. Each of the time masters includes a time master priority responder that transmits to the management master a priority response frame after receiving the priority request frame from the management master (and a time master highest priority processor that changes the priority thereof to the highest priority when the highest priority notification frame is received from the management master. The grandmaster transmits, to each time master, a time notification frame for synchronization of a time of the time master.

A method is provided for synchronizing a source device with a sink device. The source device transmits a stream of packets to the sink device. The source device receives feedback from the sink device indicating packet arrival times of the packets at the sink device. Based on the feedback, in some aspects, the source device determines an average time shift in the packet arrival times at the sink device, wherein the average time shift is relative to expected packet arrival times of the packets at the sink device. In some such aspects, the source device detects that the average time shift exceeds a threshold, and in response to the detecting, adjusts a streaming time of the stream of packets to synchronize, within a predefined tolerance, the source device with the sink device.

A power amplifier module can include one or more switches, a coupler module, input signal pins, and a controller having first and second output terminals. The input signal pins can receive a voltage input/output signal, a clock input signal, and a data input signal. The controller can (i) set a mode of the one or more switches using a synchronous communication protocol in which the controller outputs a synchronous clock signal on the first output terminal and a data signal on the second output terminal, when the power amplifier module is in a first operating mode, or (ii) set a mode of the coupler module using an asynchronous communication protocol in which the controller outputs a first asynchronous control signal on the first output terminal and a second asynchronous control signal on the second output terminal, when the power amplifier module is in a second operating mode.

Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ/bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications.

Method and system for managing the reception of data frames, scheduled statically and periodically, a frame includes a header provided with an identifier (id) of the frame and an index (index) representing the occurrence of the frame in a hyper-period.

It is made possible to favorably perform signal transfer between a plurality of daisy-chain-connected devices. There is a communication line for performing communication between a first electronic device and a second electronic device. A data generating section generates first data to be transmitted to the first electronic device. Then, a data input section inputs the first data to a first position on the communication line. In addition, a first data suppressing section is provided at a second position on the communication line, the second position being closer to the second electronic device than the first position is, and the first data suppressing section prevents the first data from being sent to the second electronic device.

A balancing circuit which may compensate for bandwidth attenuation introduced by interference between signals includes an amplifying circuit, a rising edge detection circuit and/or a falling edge detection circuit. By means of detecting the rising/falling edge of an original signal, the resulting pulse signal contains the phase information of a single “0” bit and a single “1” bit in the original signal, thus the phase of a rising edge or the phase of a falling edge of the original signal may be compensated respectively, so as to compensate for the high-frequency attenuation caused by interference between signals.

A method for synchronizing networks is disclosed. A first wired communication system having a first time base is set up in a first network. A second wired communication system having a second time base is set up in a second network. The first network and the second network are connected to a wireless communication system via a first translation unit and a second translation unit, respectively. The first translation unit and the second translation unit are synchronized to one another according to a third time base of the wireless communication system independently of the first time base and the second time base. A third synchronization message is transmitted from the first translation unit to the second translation unit. A transmission time for the third synchronization message in the third time base is determined and is used to synchronize the second time base to the first time base.